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authorAaron Durbin <adurbin@chromium.org>2017-06-08 11:00:23 -0500
committerAaron Durbin <adurbin@chromium.org>2017-06-09 18:28:57 +0200
commit93d5f40be51fc118a3b303f1fa515950f883f958 (patch)
tree9310b4fa0900bfffb99c2def14859becf0e074a5 /src/soc
parentefc92a86c2826f6fbac8c9c6098eb114c75bf9dd (diff)
downloadcoreboot-93d5f40be51fc118a3b303f1fa515950f883f958.tar.xz
soc/intel/skylake: Cache the MMIO BIOS region
If the boot media is memory mapped temporarily mark it as write protect MTRR type so that memory-mapped accesses are faster. Depthcharge payload loading was sped up by 75ms using this. Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/skylake/cpu.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index dddc1c3c7e..d1ed146c1b 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -34,6 +34,7 @@
#include <cpu/x86/name.h>
#include <cpu/x86/smm.h>
#include <delay.h>
+#include <intelblocks/fast_spi.h>
#include <pc80/mc146818rtc.h>
#include <soc/cpu.h>
#include <soc/msr.h>
@@ -569,6 +570,12 @@ static void soc_post_cpus_init(void *unused)
{
if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0)
printk(BIOS_ERR, "MTRR programming failure\n");
+
+ /* Temporarily cache the memory-mapped boot media. */
+ if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&
+ IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
+ fast_spi_cache_bios_region();
+
x86_mtrr_check();
}