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authorVladimir Serbinenko <phcoder@gmail.com>2014-11-09 03:51:32 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2015-05-26 20:31:41 +0200
commit9bb5c5c402fa26b9726019abc70c580d874bdfef (patch)
tree37234e5351ad813023cf8e4f1e06dc88af159f07 /src/soc
parent8104da771c579a092c576318509fe25df074f1ec (diff)
downloadcoreboot-9bb5c5c402fa26b9726019abc70c580d874bdfef.tar.xz
acpigen: Remove all explicit length tracking
Change-Id: I88248d78c01b4b4e42a097889b5f4ddfdac3d966 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7367 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/broadwell/acpi.c20
-rw-r--r--src/soc/intel/fsp_baytrail/acpi.c14
2 files changed, 13 insertions, 21 deletions
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index 153831b5ee..67220c5829 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -365,34 +365,30 @@ static acpi_tstate_t tss_table_coarse[] = {
{ 13, 125, 0, 0x19, 0 },
};
-static int generate_T_state_entries(int core, int cores_per_package)
+static void generate_T_state_entries(int core, int cores_per_package)
{
- int len;
-
/* Indicate SW_ALL coordination for T-states */
- len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
+ acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
/* Indicate FFixedHW so OS will use MSR */
- len += acpigen_write_empty_PTC();
+ acpigen_write_empty_PTC();
/* Set a T-state limit that can be modified in NVS */
- len += acpigen_write_TPC("\\TLVL");
+ acpigen_write_TPC("\\TLVL");
/*
* CPUID.(EAX=6):EAX[5] indicates support
* for extended throttle levels.
*/
if (cpuid_eax(6) & (1 << 5))
- len += acpigen_write_TSS_package(
+ acpigen_write_TSS_package(
ARRAY_SIZE(tss_table_fine), tss_table_fine);
else
- len += acpigen_write_TSS_package(
+ acpigen_write_TSS_package(
ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
-
- return len;
}
-static int generate_C_state_entries(void)
+static void generate_C_state_entries(void)
{
device_t dev = SA_DEV_ROOT;
config_t *config = dev->chip_info;
@@ -411,7 +407,7 @@ static int generate_C_state_entries(void)
}
/* Generate C-state tables */
- return acpigen_write_CST_package(map, ARRAY_SIZE(map));
+ acpigen_write_CST_package(map, ARRAY_SIZE(map));
}
static int calculate_power(int tdp, int p1_ratio, int ratio)
diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c
index e32d3dec7e..1a0c0ceddb 100644
--- a/src/soc/intel/fsp_baytrail/acpi.c
+++ b/src/soc/intel/fsp_baytrail/acpi.c
@@ -361,24 +361,20 @@ static acpi_tstate_t baytrail_tss_table[] = {
{ 13, 125, 0, 0x12, 0 },
};
-static int generate_T_state_entries(int core, int cores_per_package)
+static void generate_T_state_entries(int core, int cores_per_package)
{
- int len;
-
/* Indicate SW_ALL coordination for T-states */
- len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
+ acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
/* Indicate FFixedHW so OS will use MSR */
- len += acpigen_write_empty_PTC();
+ acpigen_write_empty_PTC();
/* Set NVS controlled T-state limit */
- len += acpigen_write_TPC("\\TLVL");
+ acpigen_write_TPC("\\TLVL");
/* Write TSS table for MSR access */
- len += acpigen_write_TSS_package(
+ acpigen_write_TSS_package(
ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table);
-
- return len;
}
static int calculate_power(int tdp, int p1_ratio, int ratio)