diff options
author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:21:41 -0500 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:32:49 +0200 |
commit | 9e6d143a82a852ddfa64f20ceb8695939c1dace1 (patch) | |
tree | 147ee77b05213ace8941dbebe360df972f026517 /src/soc | |
parent | c159bb0d76af801bca405e729c5f4b97a18a5a1d (diff) | |
download | coreboot-9e6d143a82a852ddfa64f20ceb8695939c1dace1.tar.xz |
soc/intel/broadwell: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I99d909ee72c3abebb1e9c8ebf44137465264bf0d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15673
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r-- | src/soc/intel/broadwell/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/intel/broadwell/elog.c | 4 | ||||
-rw-r--r-- | src/soc/intel/broadwell/include/soc/pm.h | 14 | ||||
-rw-r--r-- | src/soc/intel/broadwell/refcode.c | 2 | ||||
-rw-r--r-- | src/soc/intel/broadwell/romstage/power_state.c | 17 | ||||
-rw-r--r-- | src/soc/intel/broadwell/romstage/raminit.c | 6 | ||||
-rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 6 | ||||
-rw-r--r-- | src/soc/intel/broadwell/smihandler.c | 20 | ||||
-rw-r--r-- | src/soc/intel/broadwell/xhci.c | 3 |
9 files changed, 32 insertions, 41 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 1c29d77d2d..545eb62058 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -7,6 +7,7 @@ if SOC_INTEL_BROADWELL config CPU_SPECIFIC_OPTIONS def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_BOOTBLOCK_X86_32 select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index 3252c0d5d5..07425c6e6c 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -92,7 +92,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps) elog_add_event(ELOG_TYPE_PWROK_FAIL); /* TCO Timeout */ - if (ps->prev_sleep_state != 3 && + if (ps->prev_sleep_state != ACPI_S3 && ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET); @@ -113,7 +113,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps) elog_add_event(ELOG_TYPE_SYSTEM_RESET); /* ACPI Wake Event */ - if (ps->prev_sleep_state != SLEEP_STATE_S0) + if (ps->prev_sleep_state != ACPI_S0) elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); } diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index 3f5bc40809..18004fa77d 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -16,6 +16,8 @@ #ifndef _BROADWELL_PM_H_ #define _BROADWELL_PM_H_ +#include <arch/acpi.h> + /* ACPI_BASE_ADDRESS / PMBASE */ #define PM1_STS 0x00 @@ -34,14 +36,6 @@ #define GBL_EN (1 << 5) #define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_SHIFT 10 -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 #define GBL_RLS (1 << 2) #define BM_RLD (1 << 1) #define SCI_EN (1 << 0) @@ -113,10 +107,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#define SLEEP_STATE_S0 0 -#define SLEEP_STATE_S3 3 -#define SLEEP_STATE_S5 5 - struct chipset_power_state { uint16_t pm1_sts; uint16_t pm1_en; diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index c818752c6b..c4179f159c 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -78,7 +78,7 @@ void broadwell_run_reference_code(void) mainboard_fill_pei_data(&pei_data); broadwell_fill_pei_data(&pei_data); - pei_data.boot_mode = acpi_is_wakeup_s3() ? SLEEP_STATE_S3 : 0; + pei_data.boot_mode = acpi_is_wakeup_s3() ? ACPI_S3 : 0; pei_data.saved_data = (void *) &dummy; entry = load_reference_code(); diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 38a4109a22..cfb24182c1 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -52,17 +52,16 @@ ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) static int prev_sleep_state(struct chipset_power_state *ps) { /* Default to S0. */ - int prev_sleep_state = SLEEP_STATE_S0; + int prev_sleep_state = ACPI_S0; if (ps->pm1_sts & WAK_STS) { - switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { -#if CONFIG_HAVE_ACPI_RESUME - case SLP_TYP_S3: - prev_sleep_state = SLEEP_STATE_S3; + switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { + case ACPI_S3: + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + prev_sleep_state = ACPI_S3; break; -#endif - case SLP_TYP_S5: - prev_sleep_state = SLEEP_STATE_S5; + case ACPI_S5: + prev_sleep_state = ACPI_S5; break; } /* Clear SLP_TYP. */ @@ -70,7 +69,7 @@ static int prev_sleep_state(struct chipset_power_state *ps) } if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR)) - prev_sleep_state = SLEEP_STATE_S5; + prev_sleep_state = ACPI_S5; return prev_sleep_state; } diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 376517eaf9..488b231a96 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -55,7 +55,7 @@ void raminit(struct pei_data *pei_data) /* MRC cache found */ pei_data->saved_data_size = cache->size; pei_data->saved_data = &cache->data[0]; - } else if (pei_data->boot_mode == SLEEP_STATE_S3) { + } else if (pei_data->boot_mode == ACPI_S3) { /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); post_code(POST_RESUME_FAILURE); @@ -63,7 +63,7 @@ void raminit(struct pei_data *pei_data) } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); #if CONFIG_EC_GOOGLE_CHROMEEC - if (pei_data->boot_mode == SLEEP_STATE_S0) { + if (pei_data->boot_mode == ACPI_S0) { /* Ensure EC is running RO firmware. */ google_chromeec_check_ec_image(EC_IMAGE_RO); } @@ -104,7 +104,7 @@ void raminit(struct pei_data *pei_data) /* Basic memory sanity test */ quick_ram_check(); - if (pei_data->boot_mode != SLEEP_STATE_S3) { + if (pei_data->boot_mode != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { #if CONFIG_HAVE_ACPI_RESUME diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index c6ffe7ad68..f2b28a5a10 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -98,7 +98,7 @@ void romstage_common(struct romstage_params *params) params->pei_data->boot_mode = params->power_state->prev_sleep_state; #if CONFIG_ELOG_BOOT_COUNT - if (params->power_state->prev_sleep_state != SLEEP_STATE_S3) + if (params->power_state->prev_sleep_state != ACPI_S3) boot_count_increment(); #endif @@ -117,12 +117,12 @@ void romstage_common(struct romstage_params *params) handoff = romstage_handoff_find_or_add(); if (handoff != NULL) handoff->s3_resume = (params->power_state->prev_sleep_state == - SLEEP_STATE_S3); + ACPI_S3); else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); #if CONFIG_LPC_TPM - init_tpm(params->power_state->prev_sleep_state == SLEEP_STATE_S3); + init_tpm(params->power_state->prev_sleep_state == ACPI_S3); #endif } diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index cda94ee2fc..d4ef25b11a 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -167,18 +167,18 @@ static void southbridge_smi_sleep(void) /* Figure out SLP_TYP */ reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); - slp_typ = (reg32 >> 10) & 7; + slp_typ = acpi_sleep_from_pm1(reg32); /* Do any mainboard sleep handling */ - mainboard_smi_sleep(slp_typ-2); + mainboard_smi_sleep(slp_typ); /* USB sleep preparations */ usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ - if (slp_typ >= 5) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); + if (slp_typ >= ACPI_S3) + elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); #endif /* Clear pending GPE events */ @@ -188,22 +188,22 @@ static void southbridge_smi_sleep(void) */ switch (slp_typ) { - case SLP_TYP_S0: + case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; - case SLP_TYP_S1: + case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; - case SLP_TYP_S3: + case ACPI_S3: printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); /* Invalidate the cache before going to S3 */ wbinvd(); break; - case SLP_TYP_S4: + case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break; - case SLP_TYP_S5: + case ACPI_S5: printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); /* Turn off backlight if needed */ @@ -238,7 +238,7 @@ static void southbridge_smi_sleep(void) enable_pm1_control(SLP_EN); /* Make sure to stop executing code here for S3/S4/S5 */ - if (slp_typ > 1) + if (slp_typ >= ACPI_S3) halt(); /* diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 8453165d76..75a63cfca3 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -18,6 +18,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <arch/acpi.h> #include <arch/io.h> #include <soc/ramstage.h> #include <soc/xhci.h> @@ -146,7 +147,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) u8 *mem_base = usb_xhci_mem_base(dev); u8 is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); - if (!mem_base || slp_typ < 3) + if (!mem_base || slp_typ < ACPI_S3) return; /* Set D0 state */ |