diff options
author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-26 11:59:14 -0700 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-27 20:13:27 +0000 |
commit | a3cbbf7652db37cb6b5728028bd61139d57a5cac (patch) | |
tree | 70e7f273ed532e53232b02d1f66c679ed814678c /src/soc | |
parent | bb59f67ee8aa91eed6cc30daec3fa08d5b651f81 (diff) | |
download | coreboot-a3cbbf7652db37cb6b5728028bd61139d57a5cac.tar.xz |
intel/common/p2sb: Add common p2sb driver
Add common p2sb device driver that will use fixed resource instead
dynamic assigned by PCI enumeration.
TEST=None
Change-Id: Ie3f7036a5956e3db1662678aaf43023ff79ae10e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/p2sb.h | 22 | ||||
-rw-r--r-- | src/soc/intel/common/block/p2sb/Kconfig | 5 | ||||
-rw-r--r-- | src/soc/intel/common/block/p2sb/Makefile.inc | 1 | ||||
-rw-r--r-- | src/soc/intel/common/block/p2sb/p2sb.c | 80 |
4 files changed, 108 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h new file mode 100644 index 0000000000..8139a69b62 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_P2SB_H +#define SOC_INTEL_COMMON_BLOCK_P2SB_H + +void p2sb_unhide(void); +void p2sb_hide(void); + +#endif /* SOC_INTEL_COMMON_BLOCK_P2SB_H */ diff --git a/src/soc/intel/common/block/p2sb/Kconfig b/src/soc/intel/common/block/p2sb/Kconfig new file mode 100644 index 0000000000..7f292cde9e --- /dev/null +++ b/src/soc/intel/common/block/p2sb/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_P2SB + bool + depends on SOC_INTEL_COMMON_BLOCK_PCR + help + Intel Processor common P2SB driver diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc new file mode 100644 index 0000000000..d78714b03e --- /dev/null +++ b/src/soc/intel/common/block/p2sb/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c new file mode 100644 index 0000000000..63b9c85613 --- /dev/null +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <rules.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <intelblocks/p2sb.h> + +#define P2SB_E0 0xe0 +#define HIDE_BIT (1 << 0) + +static void p2sb_set_hide_bit(int hide) +{ + struct device *dev; + const uint16_t reg = P2SB_E0 + 1; + const uint8_t mask = HIDE_BIT; + uint8_t val; + + dev = PCH_DEV_P2SB; + + val = pci_read_config8(dev, reg); + val &= ~mask; + if (hide) + val |= mask; + pci_write_config8(dev, reg, val); +} + +void p2sb_unhide(void) +{ + p2sb_set_hide_bit(0); +} + +void p2sb_hide(void) +{ + p2sb_set_hide_bit(1); +} + +static void read_resources(struct device *dev) +{ + /* + * There's only one resource on the P2SB device. It's also already + * manually set to a fixed address in earlier boot stages. + */ + mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB); +} + +static const struct device_operations device_ops = { + .read_resources = read_resources, + .set_resources = DEVICE_NOOP, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_APL_P2SB, + PCI_DEVICE_ID_INTEL_GLK_P2SB, + PCI_DEVICE_ID_INTEL_CNL_P2SB, + 0, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; |