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authorAaron Durbin <adurbin@chromium.org>2016-02-24 19:00:03 -0600
committerAaron Durbin <adurbin@chromium.org>2016-02-26 02:16:38 +0100
commita513519df0084cb1f22339e5c156e95e435f1c0e (patch)
tree746b8cd73db36df210912d869f3c9ddd72e5295d /src/soc
parentbe7cbdcc9df8028b129dd155400ae0fe8f236351 (diff)
downloadcoreboot-a513519df0084cb1f22339e5c156e95e435f1c0e.tar.xz
soc/intel/apollolake: provide function to set up uart pads and controller
Instead of pushing the same code into each mainboard for configuring the the UART pads and initializing the host contoller provide a function to perform all the actions on behalf of the mainboard. The set of pads configured is dictated by the CONFIG_UART_FOR_CONSOLE Kconfig option. Change-Id: I06c499c7ee056b970468e0386d4bb1bc26537247 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13792 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/include/soc/uart.h3
-rw-r--r--src/soc/intel/apollolake/uart_early.c32
2 files changed, 34 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
index fd535fba23..16f09b14e0 100644
--- a/src/soc/intel/apollolake/include/soc/uart.h
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -25,4 +25,7 @@
void lpss_console_uart_init(void);
+/* Initialize the console UART including the pads for the configured UART. */
+void soc_console_uart_init(void);
+
#endif /* _SOC_APOLLOLAKE_UART_H_ */
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
index d3b1d80fc3..4ee4a38607 100644
--- a/src/soc/intel/apollolake/uart_early.c
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -22,12 +22,21 @@ static void lpss_uart_write(uint16_t reg, uint32_t val)
write32((void *)base, val);
}
+static inline int invalid_uart_for_console(void)
+{
+ /* There are actually only 2 UARTS, and they are named UART1 and
+ * UART2. They live at pci functions 1 and 2 respectively. */
+ if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1)
+ return 1;
+ return 0;
+}
+
void lpss_console_uart_init(void)
{
uint32_t clk_sel;
device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
- if (CONFIG_UART_FOR_CONSOLE > 2)
+ if (invalid_uart_for_console())
return;
/* Enable BAR0 for the UART -- this is where the 8250 registers hide */
@@ -59,3 +68,24 @@ unsigned int uart_platform_refclk(void)
/* That's within 0.5% of the actual value we've set earlier */
return 115200 * 16;
}
+
+static const struct pad_config uart_gpios[] = {
+ PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */
+ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */
+ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */
+ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */
+};
+
+void soc_console_uart_init(void)
+{
+ /* Get a 0-based pad index. See invalid_uart_for_console() above. */
+ const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;
+
+ if (invalid_uart_for_console())
+ return;
+
+ /* Configure the 2 pads per UART. */
+ gpio_configure_pads(&uart_gpios[pad_index * 2], 2);
+
+ lpss_console_uart_init();
+}