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authorBrandon Breitenstein <brandon.breitenstein@intel.com>2016-11-17 12:23:04 -0800
committerMartin Roth <martinroth@google.com>2016-11-21 23:43:28 +0100
commitc6ec8dd1cb2303f7f7a71f0f494a6fc30b93dff4 (patch)
tree0fee838b6730bdb4faeaafcb9d6560f898e936d3 /src/soc
parent5c325491ca2f791c46b2b3ca34f4ad1c750ac6f4 (diff)
downloadcoreboot-c6ec8dd1cb2303f7f7a71f0f494a6fc30b93dff4.tar.xz
fsp2_0: implement stage cache for silicon init
Stage cache will save ~20ms on S3 resume for apollolake platforms. Implementing the cache in ramstage to save silicon init and reload it on resume. This patch adds passing S3 status to silicon init in order to verify that the wake is from S3 and not for some other reason. This patch also includes changes needed for quark and skylake platforms that require fsp 2.0. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for reef and tested boot and S3 resume path saving 20ms Change-Id: I99dc93c1d7a7d5cf8d8de1aa253a326ec67f05f6 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/17460 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/chip.c5
-rw-r--r--src/soc/intel/quark/chip.c6
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c8
3 files changed, 16 insertions, 3 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 12aea77289..ef5908cc36 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -25,6 +25,7 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <romstage_handoff.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/intel/common/vbt.h>
@@ -259,6 +260,7 @@ static void set_power_limits(void)
static void soc_init(void *data)
{
struct global_nvs_t *gnvs;
+ struct romstage_handoff *handoff;
/* Save VBT info and mapping */
vbt = vbt_get(&vbt_rdev);
@@ -267,7 +269,8 @@ static void soc_init(void *data)
* default policy that doesn't honor boards' requirements. */
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
- fsp_silicon_init();
+ handoff = romstage_handoff_find_or_add();
+ fsp_silicon_init(handoff->s3_resume);
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index 77fb1fda0c..150df1272c 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -17,6 +17,7 @@
#include <assert.h>
#include <console/console.h>
#include <device/device.h>
+#include <romstage_handoff.h>
#include <soc/ramstage.h>
#include <soc/reg_access.h>
@@ -101,6 +102,8 @@ static const struct reg_script thermal_init_script[] = {
static void chip_init(void *chip_info)
{
+ struct romstage_handoff *handoff;
+
/* Validate the temperature settings */
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255);
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS
@@ -117,7 +120,8 @@ static void chip_init(void *chip_info)
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
/* Perform silicon specific init. */
- fsp_silicon_init();
+ handoff = romstage_handoff_find_or_add();
+ fsp_silicon_init(handoff->s3_resume);
}
static void pci_domain_set_resources(device_t dev)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 49569d9617..582cdbf31d 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -25,6 +25,7 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <romstage_handoff.h>
#include <soc/acpi.h>
#include <soc/interrupt.h>
#include <soc/irq.h>
@@ -34,8 +35,13 @@
void soc_init_pre_device(void *chip_info)
{
+ struct romstage_handoff *handoff;
+
+ /* Get S3 status to pass to silicon init. */
+ handoff = romstage_handoff_find_or_add();
+
/* Perform silicon specific init. */
- fsp_silicon_init();
+ fsp_silicon_init(handoff->s3_resume);
}
static void pci_domain_set_resources(device_t dev)