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| author | Furquan Shaikh <furquan@google.com> | 2016-06-20 16:08:42 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-06-21 19:57:48 +0200 |
| commit | cad9b631365c0aa3f917455c3dd44edc3e0d21d4 (patch) | |
| tree | b4781869c80b80753da31b5993f314a9ad581b87 /src/soc | |
| parent | bd205419f10e46785fc783244e9395c9e0aa47ac (diff) | |
| download | coreboot-cad9b631365c0aa3f917455c3dd44edc3e0d21d4.tar.xz | |
intel/apollolake: Disable setting of EISS bit in FSP
chrome-os-partner:54589
Change-Id: I5bdd417ed2f7ec013aeb8a0d4a9de57b1ad564a1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15276
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 4fa4ce4b6d..dd4a0a56e8 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -138,6 +138,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->P2sbBase = P2SB_BAR; silconfig->IshEnable = cfg->integrated_sensor_hub_enable; + + /* Disable setting of EISS bit in FSP. */ + silconfig->SpiEiss = 0; } struct chip_operations soc_intel_apollolake_ops = { |