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authorGarrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>2018-03-14 12:01:36 -0500
committerAaron Durbin <adurbin@chromium.org>2018-03-15 15:45:58 +0000
commite7513e0d5c418d8f43621c1fb3818c435fa6daa5 (patch)
tree4d17c769ce69651f4be54d9678b5691a757a6563 /src/soc
parent7de8503d76e09336bac0b77fc38e6715f258c774 (diff)
downloadcoreboot-e7513e0d5c418d8f43621c1fb3818c435fa6daa5.tar.xz
soc/amd/stoneyridge: Call sb_acpi_mmio_decode()
Call function sb_acpi_mmio_decode() from bootblock_fch_early_init(). This enables decoding of the FCH ACPI MMIO regions 0xfed80000 - 0xfed81fff. This is another step to moving AGESA out of the bootblock for StoneyRidge BUG=b:74586747 BRANCH=master TEST=Build and boot on Grunt. Change-Id: I8cf329e5cd2002b225742fefa5c1ddd2598de674 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25161 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index bb3157d395..e05b7dd764 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -559,6 +559,7 @@ void bootblock_fch_early_init(void)
sb_enable_rom();
sb_lpc_port80();
sb_lpc_decode();
+ sb_acpi_mmio_decode();
}
void sb_enable(device_t dev)