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authorLee Leahy <leroy.p.leahy@intel.com>2016-03-03 15:52:25 -0800
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-03-08 16:40:40 +0100
commite99e2b65cfc594ecfa56cb12660f731a6f88a57a (patch)
tree59c9fe4902346923e2e83ed1f19200af79315bd4 /src/soc
parentf466ea97bf716d47b4765d3c2df24ec14572a699 (diff)
downloadcoreboot-e99e2b65cfc594ecfa56cb12660f731a6f88a57a.tar.xz
soc/intel/quark: Add the UPD support for SiliconInit
Add the routines to handle the UPDs for SiliconInit. Currently no support is required. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful if coreboot calls SiliconInit Change-Id: I5176ab4b1ea7681c3095f102a86f4b614366c0fc Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/quark/chip.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index 3e11225b45..eb326d7fa6 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -54,3 +54,30 @@ struct chip_operations soc_intel_quark_ops = {
.init = &chip_init,
.enable_dev = chip_enable_dev,
};
+
+void soc_silicon_init_params(SILICON_INIT_UPD *params)
+{
+ struct soc_intel_quark_config *config;
+ device_t dev;
+
+ /* Locate the configuration data from devicetree.cb */
+ dev = dev_find_slot(0, LPC_DEV_FUNC);
+ if (!dev) {
+ printk(BIOS_ERR,
+ "Error! Device (PCI:0:%02x.%01x) not found, "
+ "soc_silicon_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC,
+ PCI_FUNCTION_NUMBER_QNC_LPC);
+ return;
+ }
+ config = dev->chip_info;
+
+ /* Set the parameters for SiliconInit */
+// printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n");
+}
+
+void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
+ SILICON_INIT_UPD *new)
+{
+ /* Display the parameters for SiliconInit */
+// printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
+}