diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-09-03 16:05:59 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-08 11:33:57 +0000 |
| commit | 0c66e866c95758c0e5557581a3af2cef4743c4ff (patch) | |
| tree | 0f5d183354d66fd4ad43e9b7d4fb60a406b553da /src/soc | |
| parent | 1c2de9fc3df6c5994db7bf2ee613aeb020b9b9db (diff) | |
| download | coreboot-0c66e866c95758c0e5557581a3af2cef4743c4ff.tar.xz | |
skylake: Clean up chip.h
Remove config options that do not apply and are unused on skylake.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Ic410f8e6b8ecc06d6f4fb1f229017df18c6045f3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3224b89e310909c2836ef2c669c6b2ee826b1b28
Original-Change-Id: I2b4fe85f78480eac5635e78ce4e848f73967bd27
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297740
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11563
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 33 |
1 files changed, 7 insertions, 26 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index e962b37f47..9b43b7fa2d 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -60,23 +60,6 @@ struct soc_intel_skylake_config { uint32_t gen3_dec; uint32_t gen4_dec; - /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; - - /* Force root port ASPM configuration with port bitmap */ - uint8_t pcie_port_force_aspm; - - /* Enable ADSP power gating features */ - uint8_t adsp_d3_pg_enable; - uint8_t adsp_sram_pg_enable; - - /* - * Clock Disable Map: - * [21:16] = CLKOUT_PCIE# 5-0 - * [24] = CLKOUT_ITPXDP - */ - uint32_t icc_clock_disable; - /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -100,15 +83,6 @@ struct soc_intel_skylake_config { u32 gpu_cpu_backlight; u32 gpu_pch_backlight; - /* - * Graphics CD Clock Frequency - * 0 = 337.5MHz - * 1 = 450MHz - * 2 = 540MHz - * 3 = 675MHz - */ - int cdclk; - /* Enable S0iX support */ int s0ix_enable; @@ -167,6 +141,13 @@ struct soc_intel_skylake_config { /* Audio related */ u8 EnableAzalia; u8 DspEnable; + + /* + * I/O Buffer Ownership: + * 0: HD-A Link + * 1 Shared, HD-A Link and I2S Port + * 3: I2S Ports + */ u8 IoBufferOwnership; /* Trace Hub function */ |