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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-10-31 14:52:20 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-03 06:15:35 +0000 |
commit | 0d6ddf8da7632e775dde92c9114ac6ace5ca5f14 (patch) | |
tree | 67b37afc2c6bc3cfaa3750a87394c5b056067137 /src/soc | |
parent | ea2bec2c4b1a986b059147506c99a202d5c8fad3 (diff) | |
download | coreboot-0d6ddf8da7632e775dde92c9114ac6ace5ca5f14.tar.xz |
cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
The x86 timers are a bit of a mess. Cases where different stages use
different counters and timestamps use different counters from udelays.
The original intention was to only flip TSC_CONSTANT_RATE Kconfig
to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those
counters do run with a constant rate but we just lack tsc_freq_mhz()
implementation for three platforms.
Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a
slow run of calibrate_tsc_with_pit(). This is easy enough to fix with
followup implementation of tsc_freq_mhz() for the platforms.
Implementations with LAPIC_MONOTONIC_TIMER typically will not have
tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However,
as they don't use TSC for udelay() the slow calibrate_tsc_with_pit()
is avoided.
Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900
claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch
that romstage to use UDELAY_TSC.
Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r-- | src/soc/amd/picasso/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/intel/apollolake/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/intel/baytrail/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/intel/braswell/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/intel/broadwell/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/intel/denverton_ns/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/intel/fsp_baytrail/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/intel/fsp_broadwell_de/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/intel/icelake/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/intel/quark/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/intel/skylake/Kconfig | 1 |
12 files changed, 0 insertions, 12 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index d87d634e6a..5f9792b28a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -33,7 +33,6 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select IOAPIC select HAVE_USBDEBUG_OPTIONS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b54528f579..026f6da669 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -95,7 +95,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING if !SOC_INTEL_GLK diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index c833c5360f..397e86768c 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -27,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5053790c75..7ea01863ae 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -34,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5856ef1e50..fadbb417ae 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -27,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC select SOC_INTEL_COMMON diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 941c150892..3330a69081 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -102,7 +102,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 2aadcae584..cb3713d3b0 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -50,7 +50,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index efe12da480..5a8bec995b 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 6c74a749a4..4c50828e0d 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -24,7 +24,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select TSC_MONOTONIC_TIMER - select TSC_CONSTANT_RATE select HAVE_FSP_BIN select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SOC_INTEL_COMMON diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 993e9b2d3b..86f1ff53e0 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -53,7 +53,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index b752784d15..75f13543ca 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -34,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SOC_SETS_MSRS select SPI_FLASH - select TSC_CONSTANT_RATE select UART_OVERRIDE_REFCLK select UDELAY_TSC select UNCOMPRESSED_RAMSTAGE diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f9f6f9302b..d4720a21be 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -76,7 +76,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC |