diff options
| author | Marc Jones <marcj303@gmail.com> | 2017-09-28 22:37:07 -0600 |
|---|---|---|
| committer | Marc Jones <marc@marcjonesconsulting.com> | 2017-10-03 17:56:37 +0000 |
| commit | 29922a540922550b80ba76a821c85eae328899cc (patch) | |
| tree | 648269828d8230f13d53ec343148b4a63c7a3bc0 /src/soc | |
| parent | 4460e8fc56ce95dd65dc1ceb6c362aa132f227b9 (diff) | |
| download | coreboot-29922a540922550b80ba76a821c85eae328899cc.tar.xz | |
soc/amd/stoneyridge: Wait for UART to be ready
The Stoney Ridge UART and AMBA devices must be powered and report power
and clock OK prior to using the coreboot serial console. The code used
to have a delay to wait for the power and clock, but didn't check the
OK bits. This caused long delays on a reboot, as each byte would time out
until the console was reset again at romstage.
This change also removes the UART reset. The device has just been
powered and is in reset already. Testing indicates the reset isn't
needed.
BUG=b:65853981
TEST=Boot to Chrome OS, run the reboot command, verify that the long
delay is gone.
Change-Id: I410700df5df255d20b8e5d192c72241dd44cf676
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21731
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/early_setup.c | 32 |
1 files changed, 24 insertions, 8 deletions
diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index 5166a7f5e8..e5f123a151 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -23,31 +23,47 @@ #include <cbmem.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> -#include <Fch/Fch.h> #include <cpu/x86/msr.h> #include <delay.h> +/* vendor includes */ +#include <Porting.h> +#include <AGESA.h> +#include <Fch/Fch.h> + void configure_stoneyridge_uart(void) { - u8 byte; + u8 byte, byte2; + /* Power on the UART and AMBA devices */ byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2); - byte |= 1 << 3; + byte |= AOAC_PWR_ON_DEV; write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2, byte); + byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62); - byte |= 1 << 3; + byte |= AOAC_PWR_ON_DEV; write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62, byte); + + /* Set the GPIO mux to UART */ write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0); write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0); write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0); write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0); - udelay(2000); - /* reset UART */ - write8((void *)APU_UART0_BASE + (0x2000 * CONFIG_UART_FOR_CONSOLE) - + 0x88, 0x01); + /* Wait for the UART and AMBA devices to indicate power and clock OK */ + do { + udelay(100); + byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG57 + + CONFIG_UART_FOR_CONSOLE * 2); + byte &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE); + byte2 = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + + FCH_AOAC_REG63); + byte2 &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE); + } while (!((byte == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)) && + (byte2 == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)))); + } void sb_pci_port80(void) |