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authorRaul E Rangel <rrangel@chromium.org>2020-05-01 14:04:08 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-05-05 12:59:33 +0000
commit314c716aff9895221f1f5b8bef4d3889a7749c0a (patch)
treea1520b205e0f624a9e235433d3d7f7129369ca52 /src/soc
parent65cc80f740a736d3b947268c157d3331a7cec922 (diff)
downloadcoreboot-314c716aff9895221f1f5b8bef4d3889a7749c0a.tar.xz
soc/amd/common/block/lpc: Add lpc_disable_spi_rom_sharing
If a Picasso platform wants to use GPIO 67 it must disable ROM sharing. Otherwise ROM access is incredibly slow. BUG=b:153502861 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia9ab3803a2f56f68c1164bd241fc3917a3ffcf2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/lpc.h3
-rw-r--r--src/soc/amd/common/block/lpc/Kconfig6
-rw-r--r--src/soc/amd/common/block/lpc/lpc_util.c14
3 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index dc33073d3e..1d74823542 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -10,6 +10,8 @@
/* PCI registers for D14F3 */
#define LPC_PCI_CONTROL 0x40
#define LEGACY_DMA_EN BIT(2)
+#define VW_ROM_SHARING_EN BIT(3)
+#define EXT_ROM_SHARING_EN BIT(4)
#define LPC_IO_PORT_DECODE_ENABLE 0x44
#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0)
@@ -148,6 +150,7 @@ void lpc_tpm_decode(void);
void lpc_tpm_decode_spi(void);
void lpc_enable_rom(void);
void lpc_enable_spi_prefetch(void);
+void lpc_disable_spi_rom_sharing(void);
/**
* @brief Find the size of a particular wide IO
diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig
index b0d59a55f4..3cfbfe5dcd 100644
--- a/src/soc/amd/common/block/lpc/Kconfig
+++ b/src/soc/amd/common/block/lpc/Kconfig
@@ -3,3 +3,9 @@ config SOC_AMD_COMMON_BLOCK_LPC
default n
help
Select this option to use the traditional LPC-ISA bridge at D14F3.
+
+config PROVIDES_ROM_SHARING
+ bool
+ default n
+ help
+ Select this option if the LPC bridge supports ROM sharing.
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 571c6fe8ed..45b252f99b 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
+#include <assert.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci_ops.h>
@@ -300,6 +301,19 @@ void lpc_enable_spi_prefetch(void)
pci_write_config32(_LPCB_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword);
}
+void lpc_disable_spi_rom_sharing(void)
+{
+ u8 byte;
+
+ if (!CONFIG(PROVIDES_ROM_SHARING))
+ dead_code();
+
+ byte = pci_read_config8(_LPCB_DEV, LPC_PCI_CONTROL);
+ byte &= ~VW_ROM_SHARING_EN;
+ byte &= ~EXT_ROM_SHARING_EN;
+ pci_write_config8(_LPCB_DEV, LPC_PCI_CONTROL, byte);
+}
+
uintptr_t lpc_get_spibase(void)
{
u32 base;