baytrail: Add functions to peek at GPIO input values

- Add functions to peek at GPIO input pad values (need to be used from
  romstage for board ram_id GPIOs)
- Modify UART GPIOs to use existing fn-assignment function

TEST=Manual. Add debug print and verify that GPIO functions return input
values. Also, verify UART still functions in romstage.
BUG=chrome-os-partner:22865

Change-Id: Ib2e57631c127a592cfa20ab6e2184822424e9d77
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4870
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

3 files changed, 25 insertions, 5 deletions

diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h
index aae41a4bce..bdd36c104c 100644
--- a/src/soc/intel/baytrail/baytrail/gpio.h
+++ b/src/soc/intel/baytrail/baytrail/gpio.h
@@ -134,6 +134,10 @@
 #define PAD_VAL_OUTPUT_DISABLE	(1 << 1)
 #define PAD_VAL_OUTPUT_ENABLE	(0 << 1)
 
+/* pad_val[0] - Value */
+#define PAD_VAL_HIGH		(1 << 0)
+#define PAD_VAL_LOW		(0 << 0)
+
 /* pad_val reg power-on default varies by pad, and apparently can cause issues
  * if not set correctly, even if the pin isn't configured as GPIO. */
 #define PAD_VAL_DEFAULT		(PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE)
@@ -247,6 +251,8 @@ struct soc_gpio_config* mainboard_get_gpios(void);
 
 /* Functions / defines for changing GPIOs in romstage */
 /* SCORE Pad definitions. */
+#define UART_RXD_PAD			82
+#define UART_TXD_PAD			83
 #define PCU_SMB_CLK_PAD			88
 #define PCU_SMB_DATA_PAD		90
 
@@ -282,4 +288,19 @@ static inline void ssus_select_func(int pad, int func)
 	write32(pconf0_addr, reg);
 }
 
+/* These functions require that the input pad be configured as an input GPIO */
+static inline int score_get_gpio(int pad)
+{
+	uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG;
+
+	return read32(val_addr) & PAD_VAL_HIGH;
+}
+
+static inline int ssus_get_gpio(int pad)
+{
+	uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG;
+
+	return read32(val_addr) & PAD_VAL_HIGH;
+}
+
 #endif /* _BAYTRAIL_GPIO_H_ */
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c
index 8118aeb755..9ae79c9d4d 100644
--- a/src/soc/intel/baytrail/gpio.c
+++ b/src/soc/intel/baytrail/gpio.c
@@ -44,7 +44,7 @@ static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] =
         { 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
           18,  7, 11, 20, 17,  1,  8, 10, 19, 12,
            0,  2, 23, 39, 28, 27, 22, 21, 24, 25,
-          26, 51, 56, 54, 49, 55, 48, 47, 50, 58,
+          26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
           52, 53, 59, 40 };
 
 /* GPIO bank descriptions */
diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/romstage/uart.c
index dee3be95c3..e46237ac1d 100644
--- a/src/soc/intel/baytrail/romstage/uart.c
+++ b/src/soc/intel/baytrail/romstage/uart.c
@@ -32,8 +32,7 @@ void byt_config_com1_and_enable(void)
 	reg = 1;
 	pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg);
 
-	/* Set up the pads to select the UART function. RXD and TXD are
-	 * 0x520 and 0x530, respectively. */
-	write32(IO_BASE_ADDRESS + 0x520, read32(IO_BASE_ADDRESS + 0x520) | 1);
-	write32(IO_BASE_ADDRESS + 0x530, read32(IO_BASE_ADDRESS + 0x530) | 1);
+	/* Set up the pads to select the UART function */
+	score_select_func(UART_RXD_PAD, 1);
+	score_select_func(UART_TXD_PAD, 1);
 }