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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-11-10 09:59:56 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-14 17:17:06 +0000 |
| commit | 5e2e74f981ec444d326e8fa4c79396bc428ac528 (patch) | |
| tree | 6c52612e2056d75a7d3f0b610cb59adb06b21791 /src/soc | |
| parent | 7465b9dc8d9073681b5a2b8ec3ab687156f1bc2b (diff) | |
| download | coreboot-5e2e74f981ec444d326e8fa4c79396bc428ac528.tar.xz | |
amd/stoneyridge: Replace BIT(n) in southbridge
Use more descriptive #define values for the ACPI features and
register decoding.
Change-Id: Iaaf9f9bd5761001bc4bfe6b64a6c72b1f04844bd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22427
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 0d96b5f773..6ab06780c8 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -61,10 +61,11 @@ static void sb_init_acpi_ports(void) pm_write16(PM_ACPI_SMI_CMD, 0); } - /* AcpiDecodeEnable, When set, SB uses the contents of the PM registers - * at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn - */ - pm_write8(PM_ACPI_CONF, BIT(0) | BIT(1) | BIT(4) | BIT(2)); + /* Decode ACPI registers and enable standard features */ + pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | + PM_ACPI_GLOBAL_EN | + PM_ACPI_RTC_EN_EN | + PM_ACPI_TIMER_EN_EN); } void southbridge_init(void *chip_info) |