soc/amd/picasso: Change header guards from stoney to picasso

TEST=None
BUG=b:130804851

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I32b7dbeae7538884311ccfc3a0e8db63c48fe356
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

13 files changed, 39 insertions, 39 deletions

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index d1a7d30199..4f241e7b6b 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __STONEYRIDGE_CHIP_H__
-#define __STONEYRIDGE_CHIP_H__
+#ifndef __PICASSO_CHIP_H__
+#define __PICASSO_CHIP_H__
 
 #include <stddef.h>
 #include <stdint.h>
@@ -78,4 +78,4 @@ typedef struct soc_amd_stoneyridge_config config_t;
 
 extern struct device_operations pci_domain_ops;
 
-#endif /* __STONEYRIDGE_CHIP_H__ */
+#endif /* __PICASSO_CHIP_H__ */
diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h
index 15a41edce6..71fe10eb26 100644
--- a/src/soc/amd/picasso/include/soc/acpi.h
+++ b/src/soc/amd/picasso/include/soc/acpi.h
@@ -15,8 +15,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __SOC_STONEYRIDGE_ACPI_H__
-#define __SOC_STONEYRIDGE_ACPI_H__
+#ifndef __SOC_PICASSO_ACPI_H__
+#define __SOC_PICASSO_ACPI_H__
 
 #include <arch/acpi.h>
 
@@ -37,4 +37,4 @@ void southbridge_inject_dsdt(struct device *device);
 
 const char *soc_acpi_name(const struct device *dev);
 
-#endif /* __SOC_STONEYRIDGE_ACPI_H__ */
+#endif /* __SOC_PICASSO_ACPI_H__ */
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h
index 934a9f2983..d9d48ad27c 100644
--- a/src/soc/amd/picasso/include/soc/cpu.h
+++ b/src/soc/amd/picasso/include/soc/cpu.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __STONEYRIDGE_CPU_H__
-#define __STONEYRIDGE_CPU_H__
+#ifndef __PICASSO_CPU_H__
+#define __PICASSO_CPU_H__
 
 #include <device/device.h>
 
@@ -32,4 +32,4 @@
 void stoney_init_cpus(struct device *dev);
 void check_mca(void);
 
-#endif /* __STONEYRIDGE_CPU_H__ */
+#endif /* __PICASSO_CPU_H__ */
diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h
index d8774f051a..411144beb6 100644
--- a/src/soc/amd/picasso/include/soc/gpio.h
+++ b/src/soc/amd/picasso/include/soc/gpio.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __STONEYRIDGE_GPIO_H__
-#define __STONEYRIDGE_GPIO_H__
+#ifndef __PICASSO_GPIO_H__
+#define __PICASSO_GPIO_H__
 
 #define GPIO_DEVICE_NAME	"AMD0030"
 #define GPIO_DEVICE_DESC	"GPIO Controller"
@@ -305,4 +305,4 @@
 #define GPIO_2_EVENT GEVENT_8
 
 #endif /* __ACPI__ */
-#endif /* __STONEYRIDGE_GPIO_H__ */
+#endif /* __PICASSO_GPIO_H__ */
diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h
index 62575d0fb8..fb9b113c8e 100644
--- a/src/soc/amd/picasso/include/soc/i2c.h
+++ b/src/soc/amd/picasso/include/soc/i2c.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __STONEYRIDGE_I2C_H__
-#define __STONEYRIDGE_I2C_H__
+#ifndef __PICASSO_I2C_H__
+#define __PICASSO_I2C_H__
 
 #include <soc/gpio.h>
 
@@ -46,4 +46,4 @@ struct soc_amd_i2c_save {
 
 void sb_reset_i2c_slaves(void);
 
-#endif /* __STONEYRIDGE_I2C_H__ */
+#endif /* __PICASSO_I2C_H__ */
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index 612b6e871b..a63b16462b 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -14,8 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __SOC_STONEYRIDGE_IOMAP_H__
-#define __SOC_STONEYRIDGE_IOMAP_H__
+#ifndef __SOC_PICASSO_IOMAP_H__
+#define __SOC_PICASSO_IOMAP_H__
 
 /* MMIO Ranges */
 #define PSP_MAILBOX_BAR3_BASE		0xf0a00000
@@ -85,4 +85,4 @@
 #define BIOSRAM_UMA_SIZE		0xf4 /* 4 bytes */
 #define BIOSRAM_UMA_BASE		0xf8 /* 8 bytes */
 
-#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */
+#endif /* __SOC_PICASSO_IOMAP_H__ */
diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h
index 60a6ea22bb..f7df2772c5 100644
--- a/src/soc/amd/picasso/include/soc/northbridge.h
+++ b/src/soc/amd/picasso/include/soc/northbridge.h
@@ -14,8 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__
-#define __PI_STONEYRIDGE_NORTHBRIDGE_H__
+#ifndef __PI_PICASSO_NORTHBRIDGE_H__
+#define __PI_PICASSO_NORTHBRIDGE_H__
 
 #include <device/device.h>
 #include <types.h>
@@ -130,4 +130,4 @@ void set_ap_entry_ptr(void *entry);
 void set_warm_reset_flag(void);
 int is_warm_reset(void);
 
-#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */
+#endif /* __PI_PICASSO_NORTHBRIDGE_H__ */
diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h
index 08d46973c0..8ce5da623a 100644
--- a/src/soc/amd/picasso/include/soc/nvs.h
+++ b/src/soc/amd/picasso/include/soc/nvs.h
@@ -21,8 +21,8 @@
  *
  */
 
-#ifndef __SOC_STONEYRIDGE_NVS_H__
-#define __SOC_STONEYRIDGE_NVS_H__
+#ifndef __SOC_PICASSO_NVS_H__
+#define __SOC_PICASSO_NVS_H__
 
 #include <commonlib/helpers.h>
 #include <stdint.h>
@@ -64,4 +64,4 @@ typedef struct global_nvs_t {
 } __packed global_nvs_t;
 check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
 
-#endif /* __SOC_STONEYRIDGE_NVS_H__ */
+#endif /* __SOC_PICASSO_NVS_H__ */
diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h
index 02fed7ab1e..478a2cb623 100644
--- a/src/soc/amd/picasso/include/soc/pci_devs.h
+++ b/src/soc/amd/picasso/include/soc/pci_devs.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__
-#define __PI_STONEYRIDGE_PCI_DEVS_H__
+#ifndef __PI_PICASSO_PCI_DEVS_H__
+#define __PI_PICASSO_PCI_DEVS_H__
 
 #include <device/pci_def.h>
 
@@ -195,4 +195,4 @@
 #define SD_DEVFN		PCI_DEVFN(SD_DEV, SD_FUNC)
 #define SOC_SD_DEV		_SOC_DEV(SD_DEV, SD_FUNC)
 
-#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */
+#endif /* __PI_PICASSO_PCI_DEVS_H__ */
diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h
index 6ce79b424e..d8b2900fb5 100644
--- a/src/soc/amd/picasso/include/soc/romstage.h
+++ b/src/soc/amd/picasso/include/soc/romstage.h
@@ -13,9 +13,9 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __STONEYRIDGE_ROMSTAGE_H__
-#define __STONEYRIDGE_ROMSTAGE_H__
+#ifndef __PICASSO_ROMSTAGE_H__
+#define __PICASSO_ROMSTAGE_H__
 
 void mainboard_romstage_entry(int s3_resume);
 
-#endif /* __STONEYRIDGE_ROMSTAGE_H__ */
+#endif /* __PICASSO_ROMSTAGE_H__ */
diff --git a/src/soc/amd/picasso/include/soc/smbus.h b/src/soc/amd/picasso/include/soc/smbus.h
index 391084d807..c4bc28fdf2 100644
--- a/src/soc/amd/picasso/include/soc/smbus.h
+++ b/src/soc/amd/picasso/include/soc/smbus.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __STONEYRIDGE_SMBUS_H__
-#define __STONEYRIDGE_SMBUS_H__
+#ifndef __PICASSO_SMBUS_H__
+#define __PICASSO_SMBUS_H__
 
 #include <stdint.h>
 #include <soc/iomap.h>
@@ -32,4 +32,4 @@ int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val);
 int do_smbus_recv_byte(u32 mmio, u8 device);
 int do_smbus_send_byte(u32 mmio, u8 device, u8 val);
 
-#endif /* __STONEYRIDGE_SMBUS_H__ */
+#endif /* __PICASSO_SMBUS_H__ */
diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h
index 000eed8554..da32610eed 100644
--- a/src/soc/amd/picasso/include/soc/smi.h
+++ b/src/soc/amd/picasso/include/soc/smi.h
@@ -15,8 +15,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
-#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
+#ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__
+#define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__
 
 
 #define SMI_GEVENTS			24
@@ -239,4 +239,4 @@ void soc_route_sci(uint8_t event);
 void enable_smi_generation(void);
 #endif
 
-#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */
+#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index ad4040759c..fa9206e33a 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -14,8 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __STONEYRIDGE_H__
-#define __STONEYRIDGE_H__
+#ifndef __PICASSO_SB_H__
+#define __PICASSO_SB_H__
 
 #include <types.h>
 #include <device/device.h>
@@ -412,4 +412,4 @@ void i2c_soc_early_init(void);
 /* Initialize all the i2c buses that are not marked with early init. */
 void i2c_soc_init(void);
 
-#endif /* __STONEYRIDGE_H__ */
+#endif /* __PICASSO_SB_H__ */