baytrail: add reset support

Bay Trail has the following types of resets it supports:
 - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
 - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9
 - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9
 - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9
 - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to
   0xcf9 but with ETR[20] set.

While these are documented this support currently provides support
for 2nd soft reset as well as cold and warm reset.

BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted.

Change-Id: I9746e7c8aed0ffc29e7afa137798e38c5da9c888
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172710
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4878
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

5 files changed, 98 insertions, 0 deletions

diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 4cd21334fc..293ed211b5 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_MICROCODE_IN_CBFS
 	select DYNAMIC_CBMEM
 	select HAVE_SMI_HANDLER
+	select HAVE_HARD_RESET
 	select MMCONF_SUPPORT
 	select MMCONF_SUPPORT_DEFAULT
 	select RELOCATABLE_MODULES
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index b4474c05a3..9695a70c67 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -20,6 +20,8 @@ romstage-y += iosf.c
 ramstage-y += northcluster.c
 ramstage-y += ramstage.c
 ramstage-y += gpio.c
+romstage-y += reset.c
+ramstage-y += reset.c
 
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h
index 2cf1f00220..b85800af7f 100644
--- a/src/soc/intel/baytrail/baytrail/pmc.h
+++ b/src/soc/intel/baytrail/baytrail/pmc.h
@@ -26,6 +26,12 @@
 /* Memory mapped IO registers behind PMC_BASE_ADDRESS */
 #define GEN_PMCONF1	0x20
 #	define UART_EN		(1 << 24)
+#define ETR			0x48
+#	define CF9LOCK		(1 << 31)
+#	define LTR_DEF		(1 << 22)
+#	define IGNORE_HPET	(1 << 21)
+#	define CF9GR		(1 << 20)
+#	define CWORWRE		(1 << 18)
 
 /* IO Mapped registers behind ACPI_BASE_ADDRESS */
 #define TCO_RLD			0x60
@@ -37,4 +43,10 @@
 #	define TCO_TMR_HALT	(1 << 11)
 #define TCO_TMR			0x70
 
+/* I/O ports */
+#define RST_CNT			0xcf9
+#	define FULL_RST		(1 << 3)
+#	define RST_CPU		(1 << 2)
+#	define SYS_RST		(1 << 1)
+
 #endif /* _BAYTRAIL_PMC_H_ */
diff --git a/src/soc/intel/baytrail/baytrail/reset.h b/src/soc/intel/baytrail/baytrail/reset.h
new file mode 100644
index 0000000000..dbf0fd23cf
--- /dev/null
+++ b/src/soc/intel/baytrail/baytrail/reset.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BAYTRAIL_RESET_H_
+#define _BAYTRAIL_RESET_H_
+#include <reset.h>
+
+/* Bay Trail has the following types of resets:
+ * - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
+ * - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9
+ * - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9
+ * - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9
+ * - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but
+ *   with ETR[20] set.
+ */
+
+void cold_reset(void);
+void warm_reset(void);
+
+#endif /* _BAYTRAIL_RESET_H_ */
diff --git a/src/soc/intel/baytrail/reset.c b/src/soc/intel/baytrail/reset.c
new file mode 100644
index 0000000000..a421ec9018
--- /dev/null
+++ b/src/soc/intel/baytrail/reset.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <baytrail/pmc.h>
+#include <baytrail/reset.h>
+
+void cold_reset(void)
+{
+	/* S0->S5->S0 trip. */
+	outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
+}
+
+void warm_reset(void)
+{
+	/* PMC_PLTRST# asserted. */
+	outb(RST_CPU | SYS_RST, RST_CNT);
+}
+
+void soft_reset(void)
+{
+	/* Sends INIT# to CPU */
+	outb(RST_CPU, RST_CNT);
+}
+
+void hard_reset(void)
+{
+	/* Don't power cycle on hard_reset(). It's not really clear what the
+	 * semantics should be for the meaning of hard_reset(). */
+	warm_reset();
+}