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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-13 21:14:32 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-23 18:14:42 +0000 |
| commit | 7fa445e385cae66f8c696fb54cbd38dff49452c8 (patch) | |
| tree | 4e2b021cdbfcb378c4cdbb9df8dd744c7ad3ae5f /src/soc | |
| parent | cc2708797ea0a4b19da4bf4ef49459220088f432 (diff) | |
| download | coreboot-7fa445e385cae66f8c696fb54cbd38dff49452c8.tar.xz | |
soc/intel/broadwell: Move `fill_postcar_frame` to memmap.c
Other Intel northbridges have this function in this file.
Change-Id: I9f084e760ec438d662484455212b5c40a8448928
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/memmap.c | 14 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 13 |
2 files changed, 14 insertions, 13 deletions
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index e4c787a016..f7e58af598 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -3,6 +3,7 @@ /* Use simple device model for this file even in ramstage */ #define __SIMPLE_DEVICE__ +#include <arch/romstage.h> #include <cbmem.h> #include <cpu/x86/smm.h> #include <device/pci.h> @@ -43,3 +44,16 @@ void smm_region(uintptr_t *start, size_t *size) *start = tseg; *size = bgsm - tseg; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, + MTRR_TYPE_WRBACK); +} diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 3b7aa40049..83e5b73836 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -16,19 +16,6 @@ #include <soc/romstage.h> #include <soc/spi.h> -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); -} - /* Entry from cpu/intel/car/romstage.c. */ void mainboard_romstage_entry(void) { |