soc/qualcomm/ipq40xx: Enable timer

BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none

Original-Commit-Id: 35c0e6046899dc1af03736ae9fa77f9eeec7f668
Original-Change-Id: I681e92fa673c1d3aee2974a7bba5074e2bfd6e02
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333297
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

squashed:

soc/qualcomm/ipq40xx: Enable UART on ipq40xx

- BLSP/UART Clock configuration
- GPIO Configuration

BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none

Original-Commit-Id: 7bba1fc7f50e7aeb4e7b37f164e85771e53f47e6
Original-Change-Id: I474a0e97b24ac9b3f2cba599cd709b6801b08f91
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333300
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I5e31d036ee7ddcf72ed9739cef1f7f7d0ca6c427
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14667
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

7 files changed, 146 insertions, 323 deletions

diff --git a/src/soc/qualcomm/ipq40xx/clock.c b/src/soc/qualcomm/ipq40xx/clock.c
index 4d8d8e9adc..fab0c9e07a 100644
--- a/src/soc/qualcomm/ipq40xx/clock.c
+++ b/src/soc/qualcomm/ipq40xx/clock.c
@@ -31,104 +31,43 @@
 #include <soc/clock.h>
 #include <types.h>
 
-/**
- * uart_pll_vote_clk_enable - enables PLL8
- */
-void uart_pll_vote_clk_enable(unsigned int clk_dummy)
-{
-	setbits_le32(BB_PLL_ENA_SC0_REG, BIT(8));
-
-	if (!clk_dummy)
-		while ((read32(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0)
-			;
-}
-
-/**
- * uart_set_rate_mnd - configures divider M and D values
- *
- * Sets the M, D parameters of the divider to generate the GSBI UART
- * apps clock.
- */
-static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m,
-		unsigned int n)
-{
-	/* Assert MND reset. */
-	setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
-	/* Program M and D values. */
-	write32(GSBIn_UART_APPS_MD_REG(gsbi_port), MD16(m, n));
-	/* Deassert MND reset. */
-	clrbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
-}
-
-/**
- * uart_branch_clk_enable_reg - enables branch clock
- *
- * Enables branch clock for GSBI UART port.
- */
-static void uart_branch_clk_enable_reg(unsigned int gsbi_port)
-{
-	setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9));
-}
-
-/**
- * uart_local_clock_enable - configures N value and enables root clocks
- *
- * Sets the N parameter of the divider and enables root clock and
- * branch clocks for GSBI UART port.
- */
-static void uart_local_clock_enable(unsigned int gsbi_port, unsigned int n,
-					unsigned int m)
-{
-	unsigned int reg_val, uart_ns_val;
-	void *const reg = (void *)GSBIn_UART_APPS_NS_REG(gsbi_port);
-
-	/*
-	* Program the NS register, if applicable. NS registers are not
-	* set in the set_rate path because power can be saved by deferring
-	* the selection of a clocked source until the clock is enabled.
-	*/
-	reg_val = read32(reg); // REG(0x29D4+(0x20*((n)-1)))
-	reg_val &= ~(Uart_clk_ns_mask);
-	uart_ns_val =  NS(BIT_POS_31, BIT_POS_16, n, m, 5, 4, 3, 1, 2, 0, 3);
-	reg_val |= (uart_ns_val & Uart_clk_ns_mask);
-	write32(reg, reg_val);
-
-	/* enable MNCNTR_EN */
-	reg_val = read32(reg);
-	reg_val |= BIT(8);
-	write32(reg, reg_val);
-
-	/* set source to PLL8 running @384MHz */
-	reg_val = read32(reg);
-	reg_val |= 0x3;
-	write32(reg, reg_val);
-
-	/* Enable root. */
-	reg_val |= Uart_en_mask;
-	write32(reg, reg_val);
-	uart_branch_clk_enable_reg(gsbi_port);
-}
-
-/**
- * uart_set_gsbi_clk - enables HCLK for UART GSBI port
- */
-static void uart_set_gsbi_clk(unsigned int gsbi_port)
-{
-	setbits_le32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4));
-}
+#define CLOCK_UPDATE_DELAY		1000
 
 /**
  * uart_clock_config - configures UART clocks
  *
  * Configures GSBI UART dividers, enable root and branch clocks.
  */
-void uart_clock_config(unsigned int gsbi_port, unsigned int m,
-		unsigned int n, unsigned int d, unsigned int clk_dummy)
+void uart_clock_config(unsigned int blsp_uart, unsigned int m,
+		unsigned int n, unsigned int d)
 {
-	uart_set_rate_mnd(gsbi_port, m, d);
-	uart_pll_vote_clk_enable(clk_dummy);
-	uart_local_clock_enable(gsbi_port, n, m);
-	uart_set_gsbi_clk(gsbi_port);
+	int i;
+
+	/* Setup M, N & D */
+	write32(GCC_BLSP1_UART_APPS_M(blsp_uart), m);
+	write32(GCC_BLSP1_UART_APPS_N(blsp_uart), ~(n - m));
+	write32(GCC_BLSP1_UART_APPS_D(blsp_uart), ~d);
+	write32(GCC_BLSP1_UART_MISC(blsp_uart), 0);
+
+	/* Setup source sel etc. */
+	write32(GCC_BLSP1_UART_APPS_CFG_RCGR(blsp_uart),
+			0 |		/*  0: 4 SRC_DIV = Bypass */
+			0 << 8 |	/*  8:10 SRC_SEL = CxO */
+			2 << 12);	/* 13:12 Mode = Dual Edge */
+
+	/* Trigger update */
+	setbits_le32(GCC_BLSP1_UART_APPS_CMD_RCGR(blsp_uart), 1);
+
+	/* Wait for update */
+	for (i = 0; i < CLOCK_UPDATE_DELAY; i++) {
+		if (!(read32(GCC_BLSP1_UART_APPS_CMD_RCGR(blsp_uart)) & 1)) {
+			/* Updated */
+			break;
+		}
+		udelay(1);
+	}
+
+	setbits_le32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP);
 }
 
 /**
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/clock.h b/src/soc/qualcomm/ipq40xx/include/soc/clock.h
index 51cc228c71..89343f0168 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/clock.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/clock.h
@@ -34,7 +34,7 @@
 #include <soc/iomap.h>
 
 /* UART clock @ 7.3728 MHz */
-#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
 
 /* UART specific definitions */
 
@@ -205,8 +205,8 @@
 /* Uart specific clock settings */
 
 void uart_pll_vote_clk_enable(unsigned int);
-void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n,
-		unsigned int d, unsigned int clk_dummy);
+void uart_clock_config(unsigned int blsp_uart, unsigned int m, unsigned int n,
+		unsigned int d);
 void nand_clock_config(void);
 void usb_clock_config(void);
 int audio_clock_config(unsigned frequency);
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h
index 6304f71757..56aef77829 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h
@@ -69,16 +69,22 @@
 #define GPIO_MAX_NUM  68
 
 /* GPIO TLMM: Mask */
-#define GPIO_CFG_PULL_MASK    0x3
-#define GPIO_CFG_FUNC_MASK    0xF
-#define GPIO_CFG_DRV_MASK     0x7
-#define GPIO_CFG_OE_MASK      0x1
+#define GPIO_CFG_PULL_MASK	0x3
+#define GPIO_CFG_FUNC_MASK	0xF
+#define GPIO_CFG_DRV_MASK	0x7
+#define GPIO_CFG_OE_MASK	0x1
+#define GPIO_CFG_VM_MASK	0x1
+#define GPIO_CFG_OD_EN_MASK	0x1
+#define GPIO_CFG_PU_REMASKFT	0x3
 
 /* GPIO TLMM: Shift */
-#define GPIO_CFG_PULL_SHIFT   0
-#define GPIO_CFG_FUNC_SHIFT   2
-#define GPIO_CFG_DRV_SHIFT    6
-#define GPIO_CFG_OE_SHIFT     9
+#define GPIO_CFG_PULL_SHIFT	0
+#define GPIO_CFG_FUNC_SHIFT	2
+#define GPIO_CFG_DRV_SHIFT	6
+#define GPIO_CFG_OE_SHIFT	9
+#define GPIO_CFG_VM_SHIFT	11
+#define GPIO_CFG_OD_EN_SHIFT	12
+#define GPIO_CFG_PU_RES_SHIFT	13
 
 /* GPIO IO: Mask */
 #define GPIO_IO_IN_MASK       0x1
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
index 543356dcbc..0f3c6a5cfa 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
@@ -49,37 +49,36 @@
 #define clrsetbits_le32_i(addr, clear, set)  \
 	clrsetbits_le32(((void *)(addr)), (clear), (set))
 
-#define MSM_CLK_CTL_BASE    ((void *)0x00900000)
-
-#define MSM_TMR_BASE        ((void *)0x0200A000)
-#define MSM_GPT_BASE        (MSM_TMR_BASE + 0x04)
-#define MSM_DGT_BASE        (MSM_TMR_BASE + 0x24)
-
-#define GPT_REG(off)        (MSM_GPT_BASE + (off))
-#define DGT_REG(off)        (MSM_DGT_BASE + (off))
-
-#define APCS_WDT0_EN        (MSM_TMR_BASE + 0x0040)
-#define APCS_WDT0_RST       (MSM_TMR_BASE + 0x0038)
-#define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C)
-#define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C)
-
-#define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820)
-
-#define GPT_MATCH_VAL        GPT_REG(0x0000)
-#define GPT_COUNT_VAL        GPT_REG(0x0004)
-#define GPT_ENABLE           GPT_REG(0x0008)
-#define GPT_CLEAR            GPT_REG(0x000C)
-
-#define GPT1_MATCH_VAL       GPT_REG(0x00010)
-#define GPT1_COUNT_VAL       GPT_REG(0x00014)
-#define GPT1_ENABLE          GPT_REG(0x00018)
-#define GPT1_CLEAR           GPT_REG(0x0001C)
-
-#define DGT_MATCH_VAL        DGT_REG(0x0000)
-#define DGT_COUNT_VAL        DGT_REG(0x0004)
-#define DGT_ENABLE           DGT_REG(0x0008)
-#define DGT_CLEAR            DGT_REG(0x000C)
-#define DGT_CLK_CTL          DGT_REG(0x0010)
+#define GCC_CLK_CTL_REG			((void *)0x01800000u)
+#define MSM_CLK_CTL_BASE		GCC_CLK_CTL_REG
+#define GCC_CLK_BRANCH_ENA		(GCC_CLK_CTL_REG + 0x6000)
+#define		IMEM_AXI		(1 << 17)
+#define		SYS_NOC_APSS_AHB	(1 << 16)
+#define		BIMC_AXI_M0		(1 << 15)
+#define		APSS_AHB		(1 << 14)
+#define		APSS_AXI		(1 << 13)
+#define		MPM_AHB			(1 << 12)
+#define		GMEM_SYS_NOC_AXI	(1 << 11)
+#define		BLSP1_AHB		(1 << 10)
+#define		BLSP1_SLEEP		(1 << 9)
+#define		PRNG_AHB		(1 << 8)
+#define		BOOT_ROM_AHB		(1 << 7)
+#define		MSG_RAM_AHB		(1 << 6)
+#define		TLMM_AHB		(1 << 5)
+#define		TLMM			(1 << 4)
+#define		SPMI_PCNOC_AHB		(1 << 3)
+#define		CRYPTO			(1 << 2)
+#define		CRYPTO_AXI		(1 << 1)
+#define		CRYPTO_AHB		(1 << 0)
+
+#define GCNT_GLOBAL_CTRL_BASE	((void *)0x004a0000u)
+#define GCNT_CNTCR		(GCNT_GLOBAL_CTRL_BASE + 0x1000)
+#define GCNT_GLB_CNTCV_LO	(GCNT_GLOBAL_CTRL_BASE + 0x1008)
+#define GCNT_GLB_CNTCV_HI	(GCNT_GLOBAL_CTRL_BASE + 0x100c)
+#define GCNT_CNTCV_LO		(GCNT_GLOBAL_CTRL_BASE + 0x2000)
+#define GCNT_CNTCV_HI		(GCNT_GLOBAL_CTRL_BASE + 0x2004)
+
+#define GCNT_PSHOLD		((void *)0x004AB000u)
 
 /* RPM interface constants */
 #define RPM_INT           ((void *)0x63020)
@@ -88,8 +87,8 @@
 #define RPM_SIGNAL_ENTRY  ((void *)0x47C24)
 #define RPM_FW_MAGIC_NUM 0x4D505242
 
-#define TLMM_BASE_ADDR      ((void *)0x00800000)
-#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
+#define TLMM_BASE_ADDR      ((void *)0x01000000)
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 * (x))
 #define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4)
 
 /* Yes, this is not a typo... host2 is actually mapped before host1. */
@@ -100,16 +99,23 @@
 #define USB_HOST1_DWC3_BASE	0x1100C100
 #define USB_HOST1_PHY_BASE	0x110F8800
 
-#define GSBI_4			4
-#define UART1_DM_BASE         	0x12450000
-#define UART_GSBI1_BASE       	0x12440000
-#define UART2_DM_BASE		0x12490000
-#define UART_GSBI2_BASE		0x12480000
-#define UART4_DM_BASE         	0x16340000
-#define UART_GSBI4_BASE       	0x16300000
-
-#define UART2_DM_BASE           0x12490000
-#define UART_GSBI2_BASE         0x12480000
+#define UART1_DM_BASE		((void *)0x078af000)
+#define UART2_DM_BASE		((void *)0x078b0000)
+
+enum {
+	BLSP1_UART1,
+	BLSP1_UART2,
+};
+
+#define GCC_BLSP1_UART_BCR_BASE		(GCC_CLK_CTL_REG + 0x2038)
+#define GCC_BLSP1_UART_BCR(x)		(GCC_BLSP1_UART_BCR_BASE + (x) * 0xff0)
+#define GCC_BLSP1_UART_APPS_CBCR(x)	(GCC_BLSP1_UART_BCR(x) + 4)
+#define GCC_BLSP1_UART_APPS_CMD_RCGR(x)	(GCC_BLSP1_UART_APPS_CBCR(x) + 8)
+#define GCC_BLSP1_UART_APPS_CFG_RCGR(x)	(GCC_BLSP1_UART_APPS_CMD_RCGR(x) + 4)
+#define GCC_BLSP1_UART_APPS_M(x)	(GCC_BLSP1_UART_APPS_CFG_RCGR(x) + 4)
+#define GCC_BLSP1_UART_APPS_N(x)	(GCC_BLSP1_UART_APPS_M(x) + 4)
+#define GCC_BLSP1_UART_APPS_D(x)	(GCC_BLSP1_UART_APPS_N(x) + 4)
+#define GCC_BLSP1_UART_MISC(x)		(GCC_BLSP1_UART_APPS_D(x) + 4)
 
 #define GSBI1_BASE		((void *)0x12440000)
 #define GSBI2_BASE		((void *)0x12480000)
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h b/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h
index 25a06bff93..8cb0f25a8c 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h
@@ -30,7 +30,7 @@
 #ifndef __UART_DM_H__
 #define __UART_DM_H__
 
-#define PERIPH_BLK_BLSP 0
+#define PERIPH_BLK_BLSP 1
 
 #define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \
 	((value << (32 - end_pos)) >> (32 - (end_pos - start_pos)))
diff --git a/src/soc/qualcomm/ipq40xx/timer.c b/src/soc/qualcomm/ipq40xx/timer.c
index 7b8c1f0cf6..d5650ec2d9 100644
--- a/src/soc/qualcomm/ipq40xx/timer.c
+++ b/src/soc/qualcomm/ipq40xx/timer.c
@@ -32,20 +32,10 @@
 #include <soc/ipq_timer.h>
 #include <timer.h>
 
-/*
- * DGT runs at 25 MHz / 4, or 6.25 ticks per microsecond
- */
-#define DGT_MHZ_NUM	25
-#define DGT_MHZ_DEN	4
-
-#define TIMER_TICKS(us) ((DGT_MHZ_NUM*(us) + (DGT_MHZ_DEN - 1)) / DGT_MHZ_DEN)
-#define TIMER_USECS(ticks) (DGT_MHZ_DEN*(ticks) / DGT_MHZ_NUM)
+#define GCNT_FREQ_MHZ		48
 
-/* Clock divider values for the timer. */
-#define DGT_CLK_DIV_1	0
-#define DGT_CLK_DIV_2	1
-#define DGT_CLK_DIV_3	2
-#define DGT_CLK_DIV_4	3
+#define TIMER_TICKS(us)		(GCNT_FREQ_MHZ * (us))
+#define TIMER_USECS(ticks)	((ticks) / GCNT_FREQ_MHZ)
 
 /**
  * init_timer - initialize timer
@@ -53,18 +43,26 @@
 void init_timer(void)
 {
 	/* disable timer */
-	writel_i(0, DGT_ENABLE);
+	write32(GCNT_CNTCR, 0);
 
-	/* DGT uses TCXO source which is 25MHz.
-	 * The timer should run at 1/4th the frequency of TCXO
-	 * according to clock plan.
-	 * Set clock divider to 4.
-	 */
-	writel_i(DGT_CLK_DIV_4, DGT_CLK_CTL);
+	/* Reset the counters to zero */
+	write32(GCNT_GLB_CNTCV_LO, 0);
+	write32(GCNT_GLB_CNTCV_HI, 0);
 
 	/* Enable timer */
-	writel_i(0, DGT_CLEAR);
-	writel_i(DGT_ENABLE_EN, DGT_ENABLE);
+	write32(GCNT_CNTCR, 1);
+}
+
+static inline uint64_t read_gcnt_val(void)
+{
+	uint32_t hi, lo;
+
+	do {
+		hi = read32(GCNT_CNTCV_HI);
+		lo = read32(GCNT_CNTCV_LO);
+	} while (hi != read32(GCNT_CNTCV_HI));
+
+	return ((((uint64_t)hi) << 32) | lo);
 }
 
 /**
@@ -73,26 +71,15 @@ void init_timer(void)
  */
 void udelay(unsigned usec)
 {
-	uint32_t now;
-	uint32_t last;
-	uint32_t ticks;
-	uint32_t curr_ticks = 0;
-
-	/* Calculate number of ticks required. */
-	ticks = TIMER_TICKS(usec);
+	uint64_t expire;
 
-	/* Obtain the current timer value. */
-	last = readl_i(DGT_COUNT_VAL);
+	expire = read_gcnt_val() + TIMER_TICKS(usec);
 
-	/* Loop until the right number of ticks. */
-	while (curr_ticks < ticks) {
-		now = readl_i(DGT_COUNT_VAL);
-		curr_ticks += now - last;
-		last = now;
-	}
+	while (expire >= read_gcnt_val())
+		;
 }
 
 void timer_monotonic_get(struct mono_time *mt)
 {
-	mono_time_set_usecs(mt, TIMER_USECS(readl_i(DGT_COUNT_VAL)));
+	mono_time_set_usecs(mt, TIMER_USECS(read_gcnt_val()));
 }
diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c
index cb96a2655d..81b2281a86 100644
--- a/src/soc/qualcomm/ipq40xx/uart.c
+++ b/src/soc/qualcomm/ipq40xx/uart.c
@@ -44,9 +44,8 @@
 
 typedef struct {
 	void *uart_dm_base;
-	void *uart_gsbi_base;
-	unsigned uart_gsbi;
 	uart_clk_mnd_t mnd_value;
+	unsigned blsp_uart;
 	gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS];
 } uart_params_t;
 
@@ -55,28 +54,25 @@ typedef struct {
  * board/qcom/ipq40xx_cdp/ipq40xx_board_param.h
  */
 static const uart_params_t uart_board_param = {
-	.uart_dm_base = (void *)UART4_DM_BASE,
-	.uart_gsbi_base = (void *)UART_GSBI4_BASE,
-	.uart_gsbi = GSBI_4,
-	.mnd_value = { 12, 625, 313 },
-		.dbg_uart_gpio = {
-			{
-				.gpio = 10,
-				.func = 1,
-				.dir = GPIO_OUTPUT,
-				.pull = GPIO_NO_PULL,
-				.drvstr = GPIO_12MA,
-				.enable = GPIO_DISABLE
-			},
-			{
-				.gpio = 11,
-				.func = 1,
-				.dir = GPIO_INPUT,
-				.pull = GPIO_NO_PULL,
-				.drvstr = GPIO_12MA,
-				.enable = GPIO_DISABLE
-			},
-		}
+	.uart_dm_base = UART1_DM_BASE,
+	.mnd_value = { 24, 625, 313 },
+	.blsp_uart = BLSP1_UART1,
+	.dbg_uart_gpio = {
+		{
+			.gpio = 60,
+			.func = 2,
+			.dir = GPIO_INPUT,
+			.pull = GPIO_NO_PULL,
+			.enable = GPIO_ENABLE
+		},
+		{
+			.gpio = 61,
+			.func = 2,
+			.dir = GPIO_OUTPUT,
+			.pull = GPIO_NO_PULL,
+			.enable = GPIO_ENABLE
+		},
+	},
 };
 
 /**
@@ -115,84 +111,10 @@ static int valid_data = 0;
 /* Received data */
 static unsigned int word = 0;
 
-/**
- * msm_boot_uart_dm_read - reads a word from the RX FIFO.
- * @data: location where the read data is stored
- * @count: no of valid data in the FIFO
- * @wait: indicates blocking call or not blocking call
- *
- * Reads a word from the RX FIFO. If no data is available blocks if
- * @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY.
- */
- #if 0 /* Not used yet */
-static unsigned int
-msm_boot_uart_dm_read(unsigned int *data, int *count, int wait)
-{
-	static int total_rx_data = 0;
-	static int rx_data_read = 0;
-	void *base;
-	uint32_t status_reg;
-
-	base = uart_board_param.uart_dm_base;
-
-	if (data == NULL)
-		return MSM_BOOT_UART_DM_E_INVAL;
-
-	status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
-
-	/* Check for DM_RXSTALE for RX transfer to finish */
-	while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) {
-		status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
-		if (!wait)
-			return MSM_BOOT_UART_DM_E_RX_NOT_READY;
-	}
-
-	/* Check for Overrun error. We'll just reset Error Status */
-	if (readl(MSM_BOOT_UART_DM_SR(base)) &
-			MSM_BOOT_UART_DM_SR_UART_OVERRUN) {
-		writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
-			MSM_BOOT_UART_DM_CR(base));
-		total_rx_data = rx_data_read = 0;
-		msm_boot_uart_dm_init(base);
-		return MSM_BOOT_UART_DM_E_RX_NOT_READY;
-	}
-
-	/* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */
-	if (total_rx_data == 0)
-		total_rx_data =  readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base));
-
-	/* Data available in FIFO; read a word. */
-	*data = readl(MSM_BOOT_UART_DM_RF(base, 0));
-
-	/* WAR for http://prism/CR/548280 */
-	if (*data == 0)
-		return MSM_BOOT_UART_DM_E_RX_NOT_READY;
-
-	/* increment the total count of chars we've read so far */
-	rx_data_read += FIFO_DATA_SIZE;
-
-	/* actual count of valid data in word */
-	*count = ((total_rx_data < rx_data_read) ?
-			(FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) :
-			FIFO_DATA_SIZE);
-
-	/* If there are still data left in FIFO we'll read them before
-	 * initializing RX Transfer again
-	 */
-	if (rx_data_read < total_rx_data)
-		return MSM_BOOT_UART_DM_E_SUCCESS;
-
-	msm_boot_uart_dm_init_rx_transfer(base);
-	total_rx_data = rx_data_read = 0;
-
-	return MSM_BOOT_UART_DM_E_SUCCESS;
-}
-#endif
 
 void uart_tx_byte(int idx, unsigned char data)
 {
 	int num_of_chars = 1;
-	unsigned tx_data = 0;
 	void *base = uart_board_param.uart_dm_base;
 
 	/* Wait until transmit FIFO is empty. */
@@ -206,7 +128,7 @@ void uart_tx_byte(int idx, unsigned char data)
 	write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars);
 
 	/* And now write the character(s) */
-	write32(MSM_BOOT_UART_DM_TF(base, 0), tx_data);
+	write32(MSM_BOOT_UART_DM_TF(base, 0), data);
 }
 #endif /* CONFIG_SERIAL_UART */
 
@@ -230,7 +152,7 @@ static unsigned int msm_boot_uart_dm_reset(void *base)
  * msm_boot_uart_dm_init - initilaizes UART controller
  * @uart_dm_base: UART controller base address
  */
-static unsigned int msm_boot_uart_dm_init(void  *uart_dm_base)
+unsigned int msm_boot_uart_dm_init(void  *uart_dm_base)
 {
 	/* Configure UART mode registers MR1 and MR2 */
 	/* Hardware flow control isn't supported */
@@ -303,26 +225,21 @@ void uart_init(int idx)
 {
 	/* Note int idx isn't used in this driver. */
 	void *dm_base;
-	void *gsbi_base;
 
 	dm_base = uart_board_param.uart_dm_base;
 
 	if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == UART_DM_CLK_RX_TX_BIT_RATE)
 		return; /* UART must have been already initialized. */
 
-	gsbi_base = uart_board_param.uart_gsbi_base;
 	ipq_configure_gpio(uart_board_param.dbg_uart_gpio,
 			   NO_OF_DBG_UART_GPIOS);
 
 	/* Configure the uart clock */
-	uart_clock_config(uart_board_param.uart_gsbi,
+	uart_clock_config(uart_board_param.blsp_uart,
 		uart_board_param.mnd_value.m_value,
 		uart_board_param.mnd_value.n_value,
-		uart_board_param.mnd_value.d_value,
-		0);
+		uart_board_param.mnd_value.d_value);
 
-	write32(GSBI_CTRL_REG(gsbi_base),
-		GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S);
 	write32(MSM_BOOT_UART_DM_CSR(dm_base), UART_DM_CLK_RX_TX_BIT_RATE);
 
 	/* Initialize UART_DM */
@@ -335,13 +252,6 @@ void ipq40xx_uart_init(void)
 	uart_init(0);
 }
 
-#if 0 /* Not used yet */
-uint32_t uartmem_getbaseaddr(void)
-{
-	return (uint32_t)uart_board_param.uart_dm_base;
-}
-#endif
-
 /**
  * uart_tx_flush - transmits a string of data
  * @s: string to transmit
@@ -355,27 +265,6 @@ void uart_tx_flush(int idx)
 		;
 }
 
-/**
- * uart_can_rx_byte - checks if data available for reading
- *
- * Returns 1 if data available, 0 otherwise
- */
- #if 0 /* Not used yet */
-int uart_can_rx_byte(void)
-{
-	/* Return if data is already read */
-	if (valid_data)
-		return 1;
-
-	/* Read data from the FIFO */
-	if (msm_boot_uart_dm_read(&word, &valid_data, 0) !=
-	    MSM_BOOT_UART_DM_E_SUCCESS)
-		return 0;
-
-	return 1;
-}
-#endif
-
 #if IS_ENABLED(CONFIG_DRIVERS_UART)
 /**
  * ipq40xx_serial_getc - reads a character
@@ -386,10 +275,6 @@ uint8_t uart_rx_byte(int idx)
 {
 	uint8_t byte;
 
-#if 0 /* Not used yet */
-	while (!uart_can_rx_byte())
-		;	/* wait for incoming data */
-#endif
 	byte = (uint8_t)(word & 0xff);
 	word = word >> 8;
 	valid_data--;