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| author | Benjamin Doron <benjamin.doron00@gmail.com> | 2020-11-05 22:20:52 +0000 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-09 21:34:42 +0000 |
| commit | ac6565279ce30e2eed8e5fcc14f687013717c82f (patch) | |
| tree | af980479dc647103e2e3d8493ff68c65be82d08a /src/soc | |
| parent | 136380fcac333ec28574f5bfb5b43b61a919130b (diff) | |
| download | coreboot-ac6565279ce30e2eed8e5fcc14f687013717c82f.tar.xz | |
soc/intel/skylake: Enable PCH thermal depending on devicetree
Hook up PCH thermal subsystem configuration to devicetree.
Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 89eaef5b56..1e13428252 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -295,6 +295,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) dev = pcidev_path_on_root(SA_DEVFN_TS); params->Device4Enable = dev && dev->enabled; + dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); + params->PchThermalDeviceEnable = dev && dev->enabled; params->EnableTcoTimer = !config->PmTimerDisabled; tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; |