diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2014-12-04 18:12:20 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-05 21:40:25 +0100 |
| commit | bb273162641f20efaa9e019ff9404f726439a431 (patch) | |
| tree | 774719c9161930c5c8494f466692c23ce7dec78f /src/soc | |
| parent | e10108a6691c804f4b917be9a25bc8af3d7cc6a1 (diff) | |
| download | coreboot-bb273162641f20efaa9e019ff9404f726439a431.tar.xz | |
fsp_baytrail: Update microcode for Gold 3 FSP release
New microcode for Bay Trail I B2/B3 and D0 parts was released in the
Gold 3 Bay Trail FSP release.
Change the microcode size to an area instead of the exact size of the
patches. This will hopefully reduce updates to the microcode size.
Change-Id: I58b4c57a4bb0e478ffd28bd74a5de6bb61540dfe
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7647
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 10 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 2 |
2 files changed, 9 insertions, 3 deletions
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 51b6c19f82..709ff92f76 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,8 +19,14 @@ unsigned microcode[] = { -/* Size is 0x19800 - update in microcode_size.h when a patch gets changed. */ +/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ #include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 -#include "M013067331E.h" // M0130673: Baytrail I B2 / B3 +#include "M0130673322.h" // M0130673: Baytrail I B2 / B3 +#include "M0130679901.h" // M0130679: Baytrail I D0 + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h index df6082deb0..ec553146af 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h @@ -1,2 +1,2 @@ /* Maximum size of the area that the FSP will search for the correct microcode */ -#define MICROCODE_REGION_LENGTH 0x19800 +#define MICROCODE_REGION_LENGTH 0x30000 |