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authorV Sowmya <v.sowmya@intel.com>2020-05-28 22:28:25 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-06-02 07:49:24 +0000
commitbe63cf46e50b69f14b23c49d1aec6c7d243ba0fe (patch)
tree11c97e2f39b0fc310e5b0694751ba8db23083617 /src/soc
parent4b3995c25fd57ec4e76215c55d905947c9da1429 (diff)
downloadcoreboot-be63cf46e50b69f14b23c49d1aec6c7d243ba0fe.tar.xz
soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax
This change updates scs.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for wdoo. Change-Id: Ic1b5f3395a1ea8a3dd2ac6b109f9a5abe65d137f Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/jasperlake/acpi/scs.asl24
1 files changed, 12 insertions, 12 deletions
diff --git a/src/soc/intel/jasperlake/acpi/scs.asl b/src/soc/intel/jasperlake/acpi/scs.asl
index bee862db72..508fb9bd41 100644
--- a/src/soc/intel/jasperlake/acpi/scs.asl
+++ b/src/soc/intel/jasperlake/acpi/scs.asl
@@ -37,22 +37,22 @@ Scope (\_SB.PCI0) {
Method(_PS0, 0, Serialized) {
Stall (50) // Sleep 50 us
- Store(0, PGEN) // Disable PG
+ PGEN = 0 // Disable PG
/* Clear register 0x1C20/0x4820 */
SCSC (PID_EMMC)
/* Set Power State to D0 */
- And (PMCR, 0xFFFC, PMCR)
- Store (PMCR, TEMP)
+ PMCR = PMCR & 0xFFFC
+ TEMP = PMCR
}
Method(_PS3, 0, Serialized) {
- Store(1, PGEN) // Enable PG
+ PGEN = 1 // Enable PG
/* Set Power State to D3 */
- Or (PMCR, 0x0003, PMCR)
- Store (PMCR, TEMP)
+ PMCR = PMCR | 0x0003
+ TEMP = PMCR
}
Device (CARD)
@@ -90,23 +90,23 @@ Scope (\_SB.PCI0) {
Method (_PS0, 0, Serialized)
{
- Store (0, PGEN) /* Disable PG */
+ PGEN = 0 /* Disable PG */
/* Clear register 0x1C20/0x4820 */
SCSC (PID_SDX)
/* Set Power State to D0 */
- And (PMCR, 0xFFFC, PMCR)
- Store (PMCR, TEMP)
+ PMCR = PMCR & 0xFFFC
+ TEMP = PMCR
}
Method (_PS3, 0, Serialized)
{
- Store (1, PGEN) /* Enable PG */
+ PGEN = 1 /* Enable PG */
/* Set Power State to D3 */
- Or (PMCR, 0x0003, PMCR)
- Store (PMCR, TEMP)
+ PMCR = PMCR | 0x0003
+ TEMP = PMCR
}
Device (CARD)