diff options
| author | robbie zhang <robbie.zhang@intel.com> | 2015-09-11 14:25:15 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-17 14:19:32 +0000 |
| commit | c16b1fd8ac549160b2ac564ab20c6b8ef3de8afb (patch) | |
| tree | ef1e52d21a0f984421e8f0be1615f305f43f91ba /src/soc | |
| parent | a5be7fa5c14a56d8544502c54cccc43637fab258 (diff) | |
| download | coreboot-c16b1fd8ac549160b2ac564ab20c6b8ef3de8afb.tar.xz | |
Skylake: update C state latency and power numbers
The values are taken from latest BWG as well fsp src.
BRANCH=none
BUG=chrome-os-partner:45208
TEST=Built and boot on kunimitsu
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164
Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b
Original-Reviewed-on: https://chromium-review.googlesource.com/299480
Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11659
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/acpi.c | 24 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/cpu.h | 21 |
2 files changed, 27 insertions, 18 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 18cd2d94aa..5eec7c63dc 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -77,62 +77,62 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = { [C_STATE_C0] = { }, [C_STATE_C1] = { .latency = 0, - .power = 1000, + .power = C1_POWER, .resource = MWAIT_RES(0, 0), }, [C_STATE_C1E] = { .latency = 0, - .power = 1000, + .power = C1_POWER, .resource = MWAIT_RES(0, 1), }, [C_STATE_C3] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = 500, + .power = C3_POWER, .resource = MWAIT_RES(1, 0), }, [C_STATE_C6_SHORT_LAT] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 350, + .power = C6_POWER, .resource = MWAIT_RES(2, 0), }, [C_STATE_C6_LONG_LAT] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 350, + .power = C6_POWER, .resource = MWAIT_RES(2, 1), }, [C_STATE_C7_SHORT_LAT] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 200, + .power = C7_POWER, .resource = MWAIT_RES(3, 0), }, [C_STATE_C7_LONG_LAT] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 200, + .power = C7_POWER, .resource = MWAIT_RES(3, 1), }, [C_STATE_C7S_SHORT_LAT] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 200, + .power = C7_POWER, .resource = MWAIT_RES(3, 2), }, [C_STATE_C7S_LONG_LAT] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 200, + .power = C7_POWER, .resource = MWAIT_RES(3, 3), }, [C_STATE_C8] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(3), - .power = 200, + .power = C8_POWER, .resource = MWAIT_RES(4, 0), }, [C_STATE_C9] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(4), - .power = 200, + .power = C9_POWER, .resource = MWAIT_RES(5, 0), }, [C_STATE_C10] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(5), - .power = 200, + .power = C10_POWER, .resource = MWAIT_RES(6, 0), }, }; diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index c62b3080c9..8d5c2a09a6 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -35,12 +35,21 @@ #define CPU_BCLK 100 /* Latency times in units of 1024ns. */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef +#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e +#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76 +#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x94 +#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xfa +#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x14c +#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x3f2 + +/* Power in units of mW */ +#define C1_POWER 0x3e8 +#define C3_POWER 0x1f4 +#define C6_POWER 0x15e +#define C7_POWER 0xc8 +#define C8_POWER 0xc8 +#define C9_POWER 0xc8 +#define C10_POWER 0xc8 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) |