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| author | Stef van Os <stef.van.os@prodrive-technologies.com> | 2016-04-19 14:11:11 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-04-20 23:37:29 +0200 |
| commit | cccef34155b923fc256a1637b149a5249d8d6c20 (patch) | |
| tree | 883b1ec2f815f2cc9243e6e0f260fcdd6d522fa6 /src/soc | |
| parent | 57abb998a981c5545ce275e42e73e5f9022e299c (diff) | |
| download | coreboot-cccef34155b923fc256a1637b149a5249d8d6c20.tar.xz | |
intel/fsp_broadwell_de: fix SPD CBFS file type
File type for SPD in this soc is defined as CBFS_TYPE_RAW in Makefile,
but CBFS_TYPE_SPD in code.
Causes DDR SPD not to be loaded on memory down.
Tested on Prodrive Technologies Broadwell-D 1548 module:
http://prodrive-technologies.com/amc-ix5-intel-broadwell-de-platform/
Change-Id: I44525b4742b3f93d33f0c5bd9ed642c6fb06f23f
Signed-off-by: Stef van Os <stef.van.os@prodrive-technologies.com>
Reviewed-on: https://review.coreboot.org/14415
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: York Yang <york.yang@intel.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index cab4b5919c..7a9e8f5f55 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -62,16 +62,16 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT)) UpdData->MemDownCh0Dimm0SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin", CBFS_TYPE_RAW, NULL); + = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin", CBFS_TYPE_SPD, NULL); if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT)) UpdData->MemDownCh0Dimm1SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm1.bin", CBFS_TYPE_RAW, NULL); + = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm1.bin", CBFS_TYPE_SPD, NULL); if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT)) UpdData->MemDownCh1Dimm0SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm0.bin", CBFS_TYPE_RAW, NULL); + = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm0.bin", CBFS_TYPE_SPD, NULL); if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT)) UpdData->MemDownCh1Dimm1SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin", CBFS_TYPE_RAW, NULL); + = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin", CBFS_TYPE_SPD, NULL); } else { UpdData->MemDownEnable = 0; } |