intel fsp1_1: prepare for romstage vboot verification split

In order to introduce a verstage which performs vboot
verification the cache-as-ram environment needs to be
generalized and split into pieces that can be utilized
in romstage and/or verstage. Therefore, the romstage
pieces were removed from the cache-as-ram specific pieces
that are generic:

- Add fsp/car.h to house the declarations for functions in
  the cache-as-ram environment
- Only have cache_as_ram_params which are isolated form the
  cache-as-ram environment aside from FSP_INFO_HEADER.
- Hardware requirements for console initialization is done
  in the cache-as-ram specific files.
- Provide after_raminit.S which can be included from a
  romstage separated from cache-as-ram as well as one that
  is tightly coupled to the cache-as-ram environment.
- Update the fallout from the API changes in
  soc/intel/{braswell,common,skylake}.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.

Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302481
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

5 files changed, 24 insertions, 99 deletions

diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 87b1af09df..0b1eab5f04 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -31,10 +31,6 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci_def.h>
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#endif
 #include <elog.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
@@ -170,7 +166,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps)
 }
 
 /* SOC initialization before the console is enabled */
-void soc_pre_console_init(void)
+void car_soc_pre_console_init(void)
 {
 	/* Early chipset initialization */
 	program_base_addresses();
@@ -178,16 +174,12 @@ void soc_pre_console_init(void)
 }
 
 /* SOC initialization after console is enabled */
-void soc_romstage_init(struct romstage_params *params)
+void car_soc_post_console_init(void)
 {
 	/* Continue chipset initialization */
 	set_max_freq();
 	spi_init();
 
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
-	/* Ensure the EC is in the right mode for recovery */
-	google_chromeec_early_init();
-#endif
 	lpc_init();
 }
 
diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c
index 932d5c36e8..0779c55270 100644
--- a/src/soc/intel/common/raminit.c
+++ b/src/soc/intel/common/raminit.c
@@ -57,7 +57,6 @@ void raminit(struct romstage_params *params)
 	unsigned long int data;
 	EFI_PEI_HOB_POINTERS hob_ptr;
 #endif
-	struct fsp_car_context *fsp_car_context;
 
 	/*
 	 * Find and copy the UPD region to the stack so the platform can modify
@@ -69,8 +68,7 @@ void raminit(struct romstage_params *params)
 	 * region in the FSP binary.
 	 */
 	post_code(0x34);
-	fsp_car_context = params->chipset_context;
-	fsp_header = fsp_car_context->fih;
+	fsp_header = params->chipset_context;
 	vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
 					fsp_header->ImageBase);
 	printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr);
diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
index 42e624cab9..6fc569c39a 100644
--- a/src/soc/intel/common/romstage.c
+++ b/src/soc/intel/common/romstage.c
@@ -48,37 +48,22 @@
 #include <tpm.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
-/* Entry from cache-as-ram.inc. */
-asmlinkage void *romstage_main(struct cache_as_ram_params *car_params)
+asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
 {
 	void *top_of_stack;
 	struct pei_data pei_data;
-	struct fsp_car_context *fsp_car_context;
 	struct romstage_params params = {
-		.bist = car_params->bist,
 		.pei_data = &pei_data,
-		.chipset_context = car_params->chipset_context,
+		.chipset_context = fih,
 	};
 
-	fsp_car_context = car_params->chipset_context;
 	post_code(0x30);
 
-	/* Save timestamp data */
-	timestamp_init(car_params->tsc);
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	memset(&pei_data, 0, sizeof(pei_data));
 
-	/* Call into pre-console init code. */
-	soc_pre_console_init();
-	mainboard_pre_console_init();
-
-	/* Start console drivers */
-	console_init();
-
 	/* Display parameters */
-	printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist);
-	printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc);
 	printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
 		CONFIG_MMCONF_BASE_ADDRESS);
 	printk(BIOS_INFO, "Using: %s\n",
@@ -87,25 +72,11 @@ asmlinkage void *romstage_main(struct cache_as_ram_params *car_params)
 		"No Memory Support"));
 
 	/* Display FSP banner */
-	printk(BIOS_DEBUG, "FSP TempRamInit successful\n");
-	print_fsp_info(fsp_car_context->fih);
-
-	if (fsp_car_context->bootloader_car_start != CONFIG_DCACHE_RAM_BASE ||
-	    fsp_car_context->bootloader_car_end !=
-			(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) {
-		printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n",
-			CONFIG_DCACHE_RAM_BASE,
-			CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE,
-			(long)fsp_car_context->bootloader_car_start,
-			(long)fsp_car_context->bootloader_car_end);
-	}
+	print_fsp_info(fih);
 
 	/* Get power state */
 	params.power_state = fill_power_state();
 
-	/* Perform SOC specific initialization. */
-	soc_romstage_init(&params);
-
 	/*
 	 * Read and print board version.  Done after SOC romstage
 	 * in case PCH needs to be configured to talk to the EC.
@@ -125,6 +96,11 @@ asmlinkage void *romstage_main(struct cache_as_ram_params *car_params)
 	return top_of_stack;
 }
 
+void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
+{
+	return romstage_main(fih);
+}
+
 /* Entry from the mainboard. */
 void romstage_common(struct romstage_params *params)
 {
@@ -204,13 +180,8 @@ void romstage_common(struct romstage_params *params)
 		init_tpm(params->power_state->prev_sleep_state == SLEEP_STATE_S3);
 }
 
-asmlinkage void romstage_after_car(void *chipset_context)
+void after_cache_as_ram_stage(void)
 {
-	timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END);
-	printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n");
-	soc_after_temp_ram_exit();
-	soc_display_mtrrs();
-
 	/* Load the ramstage. */
 	copy_and_run();
 	die("ERROR - Failed to load ramstage!");
@@ -238,11 +209,6 @@ __attribute__((weak)) void mainboard_check_ec_image(
 #endif
 }
 
-/* Board initialization before the console is enabled */
-__attribute__((weak)) void mainboard_pre_console_init(void)
-{
-}
-
 /* Board initialization before and after RAM is enabled */
 __attribute__((weak)) void mainboard_romstage_entry(
 	struct romstage_params *params)
@@ -443,29 +409,8 @@ __attribute__((weak)) void soc_after_ram_init(struct romstage_params *params)
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
 
-/* SOC initialization after temporary RAM is disabled */
-__attribute__((weak)) void soc_after_temp_ram_exit(void)
-{
-	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* SOC initialization before the console is enabled */
-__attribute__((weak)) void soc_pre_console_init(void)
-{
-}
-
 /* SOC initialization before RAM is enabled */
 __attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params)
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
-
-/* SOC initialization after console is enabled */
-__attribute__((weak)) void soc_romstage_init(struct romstage_params *params)
-{
-	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
-	/* Ensure the EC is in the right mode for recovery */
-	google_chromeec_early_init();
-#endif
-}
diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h
index ac1d6a0d38..272679f8d9 100644
--- a/src/soc/intel/common/romstage.h
+++ b/src/soc/intel/common/romstage.h
@@ -24,17 +24,12 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <memory_info.h>
+#include <fsp/car.h>
 #include <fsp/util.h>
 #include <soc/intel/common/util.h>
 #include <soc/pei_data.h>
 #include <soc/pm.h>		/* chip_power_state */
 
-struct cache_as_ram_params {
-	uint64_t tsc;
-	uint32_t bist;
-	void *chipset_context;
-};
-
 struct romstage_params {
 	unsigned long bist;
 	struct chipset_power_state *power_state;
@@ -80,7 +75,6 @@ struct romstage_params {
 void mainboard_check_ec_image(struct romstage_params *params);
 void mainboard_memory_init_params(struct romstage_params *params,
 	MEMORY_INIT_UPD *memory_params);
-void mainboard_pre_console_init(void);
 void mainboard_romstage_entry(struct romstage_params *params);
 void mainboard_save_dimm_info(struct romstage_params *params);
 void mainboard_add_dimm_info(struct romstage_params *params,
@@ -88,18 +82,14 @@ void mainboard_add_dimm_info(struct romstage_params *params,
 			     int channel, int dimm, int index);
 void raminit(struct romstage_params *params);
 void report_memory_config(void);
-asmlinkage void romstage_after_car(void *chipset_context);
 void romstage_common(struct romstage_params *params);
-asmlinkage void *romstage_main(struct cache_as_ram_params *car_params);
+asmlinkage void *romstage_main(FSP_INFO_HEADER *fih);
 void *setup_stack_and_mtrrs(void);
 void soc_after_ram_init(struct romstage_params *params);
-void soc_after_temp_ram_exit(void);
 void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
 	MEMORY_INIT_UPD *new);
 void soc_memory_init_params(struct romstage_params *params,
 			    MEMORY_INIT_UPD *upd);
-void soc_pre_console_init(void);
 void soc_pre_ram_init(struct romstage_params *params);
-void soc_romstage_init(struct romstage_params *params);
 
 #endif /* _COMMON_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 922062610a..b21eb8a304 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -46,8 +46,15 @@
 #include <timestamp.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
-/* SOC initialization before the console is enabled */
-void soc_pre_console_init(void)
+/* SOC initialization before RAM is enabled */
+void soc_pre_ram_init(struct romstage_params *params)
+{
+	/* Prepare to initialize memory */
+	soc_fill_pei_data(params->pei_data);
+}
+
+/* SOC initialization before the console is enabled. */
+void car_soc_pre_console_init(void)
 {
 	/* System Agent Early Initialization */
 	systemagent_early_init();
@@ -56,14 +63,7 @@ void soc_pre_console_init(void)
 		pch_uart_init();
 }
 
-/* SOC initialization before RAM is enabled */
-void soc_pre_ram_init(struct romstage_params *params)
-{
-	/* Prepare to initialize memory */
-	soc_fill_pei_data(params->pei_data);
-}
-
-void soc_romstage_init(struct romstage_params *params)
+void car_soc_post_console_init(void)
 {
 	report_platform_info();
 	set_max_freq();