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authorPatrick Georgi <pgeorgi@google.com>2018-10-22 14:54:48 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-23 07:11:31 +0000
commite7864ceabc2a5b808007688b2b6fb437a154b29a (patch)
treeb198c99eca3fd82a2c6662e952cb5a7431c64b8c /src/soc
parent88030b722dfa31291aa263ff54e4d59431d4557b (diff)
downloadcoreboot-e7864ceabc2a5b808007688b2b6fb437a154b29a.tar.xz
soc/intel/apollolake: Add reset code to postcar stage
Also add a test case for that, a config taken from chromiumos with some references to binaries dropped that aren't in our blobs repo (eg audio firmware). Change-Id: I411c0bacefd9345326f26db4909921dddba28237 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/29223 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 632cb99a3b..ede565ae37 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -72,6 +72,8 @@ postcar-y += memmap.c
postcar-y += mmap_boot.c
postcar-y += spi.c
postcar-y += i2c.c
+postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c
+postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S