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authorGabe Black <gabeblack@google.com>2014-03-27 21:26:46 -0700
committerMarc Jones <marc.jones@se-eng.com>2014-12-09 20:32:18 +0100
commitec9293fb5af2c0f798a8ee6e5fead819487f1587 (patch)
treeda81aa1adae4efa68f62a2a7796c5473f671c7d0 /src/soc
parent87f3b4ea01ca90eb242dbf1a8b829d1fb3aaaa7d (diff)
downloadcoreboot-ec9293fb5af2c0f798a8ee6e5fead819487f1587.tar.xz
spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions.
They were only used internal to the SPI drivers and, according to the comment next to their prototypes, were for when the SPI controller doesn't control the chip select line directly and needs some help. BUG=None TEST=Built for link, falco, and rambi. Built and booted on peach_pit and nyan. BRANCH=None Original-Change-Id: If4622819a4437490797d305786e2436e2e70c42b Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192048 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1e2deecd9d8c6fd690c54f24e902cc7d2bab0521) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ida08cbc2be5ad09b929ca16e483c36c49ac12627 Reviewed-on: http://review.coreboot.org/7708 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/baytrail/spi.c10
-rw-r--r--src/soc/intel/fsp_baytrail/spi.c10
-rw-r--r--src/soc/nvidia/tegra124/spi.c24
-rw-r--r--src/soc/samsung/exynos5420/spi.c16
4 files changed, 10 insertions, 50 deletions
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index 7dd21e849e..64aeb9bcc9 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -327,16 +327,6 @@ void spi_release_bus(struct spi_slave *slave)
/* Handled by ICH automatically. */
}
-void spi_cs_activate(struct spi_slave *slave)
-{
- /* Handled by ICH automatically. */
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- /* Handled by ICH automatically. */
-}
-
typedef struct spi_transaction {
const uint8_t *out;
uint32_t bytesout;
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index f62164a4a2..0c3c63d8da 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -325,16 +325,6 @@ void spi_release_bus(struct spi_slave *slave)
/* Handled by ICH automatically. */
}
-void spi_cs_activate(struct spi_slave *slave)
-{
- /* Handled by ICH automatically. */
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- /* Handled by ICH automatically. */
-}
-
typedef struct spi_transaction {
const uint8_t *out;
uint32_t bytesout;
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c
index 7ad771633c..841a3c109b 100644
--- a/src/soc/nvidia/tegra124/spi.c
+++ b/src/soc/nvidia/tegra124/spi.c
@@ -212,11 +212,13 @@ static unsigned int tegra_spi_speed(unsigned int bus)
return 50000000;
}
-void spi_cs_activate(struct spi_slave *slave)
+int spi_claim_bus(struct spi_slave *slave)
{
struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs;
u32 val;
+ tegra_spi_init(slave->bus);
+
val = read32(&regs->command1);
/* select appropriate chip-select line */
@@ -230,9 +232,10 @@ void spi_cs_activate(struct spi_slave *slave)
val |= SPI_CMD1_CS_SW_VAL;
write32(val, &regs->command1);
+ return 0;
}
-void spi_cs_deactivate(struct spi_slave *slave)
+void spi_release_bus(struct spi_slave *slave)
{
struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs;
u32 val;
@@ -848,8 +851,7 @@ static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest,
spi_read_cmd[2] = (offset >> 8) & 0xff;
spi_read_cmd[3] = offset & 0xff;
- /* assert /CS */
- spi_cs_activate(spi->slave);
+ spi_claim_bus(spi->slave);
if (spi_xfer(spi->slave, spi_read_cmd,
read_cmd_bytes, NULL, 0) < 0) {
@@ -872,7 +874,7 @@ static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest,
tegra_spi_cbfs_read_exit:
/* de-assert /CS */
- spi_cs_deactivate(spi->slave);
+ spi_release_bus(spi->slave);
return (ret < 0) ? 0 : ret;
}
@@ -933,15 +935,3 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
return &channel->slave;
}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- tegra_spi_init(slave->bus);
- spi_cs_activate(slave);
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- spi_cs_deactivate(slave);
-}
diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c
index 31611e3ed6..36742a7279 100644
--- a/src/soc/samsung/exynos5420/spi.c
+++ b/src/soc/samsung/exynos5420/spi.c
@@ -133,22 +133,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
return &eslave->slave;
}
-void spi_cs_activate(struct spi_slave *slave)
+int spi_claim_bus(struct spi_slave *slave)
{
struct exynos_spi *regs = to_exynos_spi(slave)->regs;
// TODO(hungte) Add some delay if too many transactions happen at once.
clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct exynos_spi *regs = to_exynos_spi(slave)->regs;
- setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- spi_cs_activate(slave);
return 0;
}
@@ -231,7 +220,8 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytes_out,
void spi_release_bus(struct spi_slave *slave)
{
- spi_cs_deactivate(slave);
+ struct exynos_spi *regs = to_exynos_spi(slave)->regs;
+ setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);
}
static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len,