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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-03-11 07:55:24 -0800 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-05-02 22:04:54 +0200 |
| commit | eee0e229764e965996479d7eb07e6086176b8bf0 (patch) | |
| tree | 5b4e9d82b4818533633431080a7bd27b5c2025b0 /src/soc | |
| parent | 0e556326619ece4c7847ddc6ffccb19b02e22da4 (diff) | |
| download | coreboot-eee0e229764e965996479d7eb07e6086176b8bf0.tar.xz | |
soc/intel/quark: Remove UPD parameters
Remove the UPD parameters to match QuarkFsp code.
TEST=Build and run on Galileo Gen2
Change-Id: Ie4639d1f087cc2bc4387aa691eb66b640fe8faf9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14451
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/quark/chip.c | 20 | ||||
| -rw-r--r-- | src/soc/intel/quark/romstage/romstage.c | 16 |
2 files changed, 1 insertions, 35 deletions
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index eb326d7fa6..7ea8a062a1 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -55,29 +55,11 @@ struct chip_operations soc_intel_quark_ops = { .enable_dev = chip_enable_dev, }; -void soc_silicon_init_params(SILICON_INIT_UPD *params) +void soc_silicon_init_params(SILICON_INIT_UPD *upd) { - struct soc_intel_quark_config *config; - device_t dev; - - /* Locate the configuration data from devicetree.cb */ - dev = dev_find_slot(0, LPC_DEV_FUNC); - if (!dev) { - printk(BIOS_ERR, - "Error! Device (PCI:0:%02x.%01x) not found, " - "soc_silicon_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, - PCI_FUNCTION_NUMBER_QNC_LPC); - return; - } - config = dev->chip_info; - - /* Set the parameters for SiliconInit */ -// printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n"); } void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new) { - /* Display the parameters for SiliconInit */ -// printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); } diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 5bedb25b3b..93fb24b1c9 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -81,13 +81,6 @@ void soc_memory_init_params(struct romstage_params *params, } config = dev->chip_info; - /* Set the parameters for MemoryInit */ - printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); - upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? - config->PcdSmmTsegSize : 0; - upd->PcdPlatformDataBaseAddress = (UINT32)pdat_file; - upd->PcdPlatformDataMaxLen = (UINT32)pdat_file_len; - /* Display the ROM shadow data */ hexdump((void *)0x000ffff0, 0x10); } @@ -116,13 +109,4 @@ void soc_after_ram_init(struct romstage_params *params) void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new) { - /* Display the parameters for MemoryInit */ - printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); - fsp_display_upd_value("PcdSmmTsegSize", 2, - old->PcdSmmTsegSize, new->PcdSmmTsegSize); - fsp_display_upd_value("PcdPlatformDataBaseAddress", 4, - old->PcdPlatformDataBaseAddress, - new->PcdPlatformDataBaseAddress); - fsp_display_upd_value("PcdPlatformDataMaxLen", 4, - old->PcdPlatformDataMaxLen, new->PcdPlatformDataMaxLen); } |