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authorMichael Niewöhner <foss@mniewoehner.de>2020-05-07 01:32:32 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-11 08:29:28 +0000
commitf00b3375257c4128551b040f2b6a0d086c267bc9 (patch)
tree0f92a3d0f3f199e93be94a4c53a2644708638471 /src/soc
parente5ec91b393992dbdefdf7b5b6778445ddb39027e (diff)
downloadcoreboot-f00b3375257c4128551b040f2b6a0d086c267bc9.tar.xz
soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX
CB:41106 revealed that mb/intel/cedarisland already sets FSP-S UPD (see CB:40735) while the required includes are still missing in CPX. Buildbot did not fail because `ramstage.c` never was (implicitly) included. Fix this problem by making SKX/CPX share a common ramstage header for now by moving the one from SKX. Test: Build cedarisland_crb Change-Id: I9cd25edd167ec71ee98c7ffa4fa6f95ca73a75e9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h6
-rw-r--r--src/soc/intel/xeon_sp/include/soc/ramstage.h (renamed from src/soc/intel/xeon_sp/skx/include/soc/ramstage.h)0
2 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h b/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h
deleted file mode 100644
index 28e8d1a1dc..0000000000
--- a/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
-
-#include <device/device.h>
-
-extern struct pci_operations soc_pci_ops;
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h b/src/soc/intel/xeon_sp/include/soc/ramstage.h
index 18373f8884..18373f8884 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h
+++ b/src/soc/intel/xeon_sp/include/soc/ramstage.h