summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2018-11-28 12:25:54 +0100
committerDuncan Laurie <dlaurie@chromium.org>2018-11-30 21:53:00 +0000
commit0ac555e8fb2d551bfe70f87286fd73bac86c335e (patch)
treee55daa1937744ff7a81b737d35c9839da61f1eed /src/soc
parentf7d1c8d1eb651dcf1c692e33fd662500e93ad1fc (diff)
downloadcoreboot-0ac555e8fb2d551bfe70f87286fd73bac86c335e.tar.xz
soc/intel/common: Rework acpi/cpu.asl
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/acpi/cpu.asl99
-rw-r--r--src/soc/intel/cannonlake/acpi/cpu.asl40
-rw-r--r--src/soc/intel/common/block/acpi/acpi.c6
-rw-r--r--src/soc/intel/icelake/acpi/cpu.asl40
4 files changed, 46 insertions, 139 deletions
diff --git a/src/soc/intel/apollolake/acpi/cpu.asl b/src/soc/intel/apollolake/acpi/cpu.asl
index a202cebc0e..d42d1bbe51 100644
--- a/src/soc/intel/apollolake/acpi/cpu.asl
+++ b/src/soc/intel/apollolake/acpi/cpu.asl
@@ -13,106 +13,23 @@
* GNU General Public License for more details.
*/
-/* These devices are created at runtime */
-External (\_PR.CP00, DeviceObj)
-External (\_PR.CP01, DeviceObj)
-External (\_PR.CP02, DeviceObj)
-External (\_PR.CP03, DeviceObj)
-External (\_PR.CP04, DeviceObj)
-External (\_PR.CP05, DeviceObj)
-External (\_PR.CP06, DeviceObj)
-External (\_PR.CP07, DeviceObj)
+/* These come from the dynamically created CPU SSDT */
+External (\_PR.CNOT, MethodObj)
-/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
+/* Notify OS to re-read CPU tables */
Method (PNOT)
{
- If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x81) // _CST
- Notify (\_PR.CP01, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x81) // _CST
- Notify (\_PR.CP03, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CP04, 0x81) // _CST
- Notify (\_PR.CP05, 0x81) // _CST
- Notify (\_PR.CP06, 0x81) // _CST
- Notify (\_PR.CP07, 0x81) // _CST
- }
+ \_PR.CNOT (0x81)
}
-/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
+/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
- If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x80) // _PPC
- Notify (\_PR.CP01, 0x80) // _PPC
- }
- If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x80) // _PPC
- Notify (\_PR.CP03, 0x80) // _PPC
- }
- If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CP04, 0x80) // _PPC
- Notify (\_PR.CP05, 0x80) // _PPC
- Notify (\_PR.CP06, 0x80) // _PPC
- Notify (\_PR.CP07, 0x80) // _PPC
- }
+ \_PR.CNOT (0x80)
}
-/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
+/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
- If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x82) // _TPC
- Notify (\_PR.CP01, 0x82) // _TPC
- }
- If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x82) // _TPC
- Notify (\_PR.CP03, 0x82) // _TPC
- }
- If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CP04, 0x82) // _TPC
- Notify (\_PR.CP05, 0x82) // _TPC
- Notify (\_PR.CP06, 0x82) // _TPC
- Notify (\_PR.CP07, 0x82) // _TPC
- }
-}
-
-/* Return a package containing enabled processor entries */
-Method (PPKG)
-{
- If (LGreaterEqual (\PCNT, 8)) {
- Return (Package()
- {
- \_PR.CP00,
- \_PR.CP01,
- \_PR.CP02,
- \_PR.CP03,
- \_PR.CP04,
- \_PR.CP05,
- \_PR.CP06,
- \_PR.CP07
- })
- } ElseIf (LGreaterEqual (\PCNT, 4)) {
- Return (Package ()
- {
- \_PR.CP00,
- \_PR.CP01,
- \_PR.CP02,
- \_PR.CP03
- })
- } ElseIf (LGreaterEqual (\PCNT, 2)) {
- Return (Package ()
- {
- \_PR.CP00,
- \_PR.CP01
- })
- } Else {
- Return (Package ()
- {
- \_PR.CP00
- })
- }
+ \_PR.CNOT (0x82)
}
diff --git a/src/soc/intel/cannonlake/acpi/cpu.asl b/src/soc/intel/cannonlake/acpi/cpu.asl
index 79314e6a88..5f65bd8b4b 100644
--- a/src/soc/intel/cannonlake/acpi/cpu.asl
+++ b/src/soc/intel/cannonlake/acpi/cpu.asl
@@ -13,31 +13,23 @@
* GNU General Public License for more details.
*/
-/* These devices are created at runtime */
-External (\_PR.CP00, DeviceObj)
-External (\_PR.CP01, DeviceObj)
-External (\_PR.CP02, DeviceObj)
-External (\_PR.CP03, DeviceObj)
-External (\_PR.CP04, DeviceObj)
-External (\_PR.CP05, DeviceObj)
-External (\_PR.CP06, DeviceObj)
-External (\_PR.CP07, DeviceObj)
+/* These come from the dynamically created CPU SSDT */
+External (\_PR.CNOT, MethodObj)
-/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
+/* Notify OS to re-read CPU tables */
Method (PNOT)
{
- If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x81) // _CST
- Notify (\_PR.CP01, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x81) // _CST
- Notify (\_PR.CP03, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CP04, 0x81) // _CST
- Notify (\_PR.CP05, 0x81) // _CST
- Notify (\_PR.CP06, 0x81) // _CST
- Notify (\_PR.CP07, 0x81) // _CST
- }
+ \_PR.CNOT (0x81)
+}
+
+/* Notify OS to re-read CPU _PPC limit */
+Method (PPCN)
+{
+ \_PR.CNOT (0x80)
+}
+
+/* Notify OS to re-read Throttle Limit tables */
+Method (TNOT)
+{
+ \_PR.CNOT (0x82)
}
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 870e371233..0ea6cb9d70 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -436,6 +436,12 @@ void generate_cpu_entries(struct device *device)
acpigen_pop_len();
}
}
+ /* PPKG is usually used for thermal management
+ of the first and only package. */
+ acpigen_write_processor_package("PPKG", 0, cores_per_package);
+
+ /* Add a method to notify processor nodes */
+ acpigen_write_processor_cnot(cores_per_package);
}
#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
diff --git a/src/soc/intel/icelake/acpi/cpu.asl b/src/soc/intel/icelake/acpi/cpu.asl
index be6e793ab9..2981c19754 100644
--- a/src/soc/intel/icelake/acpi/cpu.asl
+++ b/src/soc/intel/icelake/acpi/cpu.asl
@@ -13,31 +13,23 @@
* GNU General Public License for more details.
*/
-/* These devices are created at runtime */
-External (\_PR.CP00, DeviceObj)
-External (\_PR.CP01, DeviceObj)
-External (\_PR.CP02, DeviceObj)
-External (\_PR.CP03, DeviceObj)
-External (\_PR.CP04, DeviceObj)
-External (\_PR.CP05, DeviceObj)
-External (\_PR.CP06, DeviceObj)
-External (\_PR.CP07, DeviceObj)
+/* These come from the dynamically created CPU SSDT */
+External (\_PR.CNOT, MethodObj)
-/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
+/* Notify OS to re-read CPU tables */
Method (PNOT)
{
- If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x81) // _CST
- Notify (\_PR.CP01, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x81) // _CST
- Notify (\_PR.CP03, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CP04, 0x81) // _CST
- Notify (\_PR.CP05, 0x81) // _CST
- Notify (\_PR.CP06, 0x81) // _CST
- Notify (\_PR.CP07, 0x81) // _CST
- }
+ \_PR.CNOT (0x81)
+}
+
+/* Notify OS to re-read CPU _PPC limit */
+Method (PPCN)
+{
+ \_PR.CNOT (0x80)
+}
+
+/* Notify OS to re-read Throttle Limit tables */
+Method (TNOT)
+{
+ \_PR.CNOT (0x82)
}