diff options
| author | Frans Hendriks <fhendriks@eltan.com> | 2018-10-31 13:58:26 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-28 11:49:35 +0000 |
| commit | 190e5bee4a75208d1975c639321f46d4425e3583 (patch) | |
| tree | cc89ddff3b8ab6793515ec30ab49e3ae1fb2ec01 /src/soc | |
| parent | 624195e45423d854f350386803544624b1b976c3 (diff) | |
| download | coreboot-190e5bee4a75208d1975c639321f46d4425e3583.tar.xz | |
src/soc/intel/braswell/include/soc/irq.h: Change PIRQ_PIC_IRQDISABLE value
Using 0 for PIRQ_PIC_IRQDISABLE might conflict with using IRQ0 as PIRQ.
Change PIRQ_PIC_IRQDISABLE value to 0x80, so value 0 is reserved for IRQ0.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29393
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/braswell/include/soc/irq.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/braswell/include/soc/irq.h b/src/soc/intel/braswell/include/soc/irq.h index 4375c20702..a2327550a9 100644 --- a/src/soc/intel/braswell/include/soc/irq.h +++ b/src/soc/intel/braswell/include/soc/irq.h @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -142,7 +143,7 @@ /* PIC IRQ settings. */ -#define PIRQ_PIC_IRQDISABLE 0x0 +#define PIRQ_PIC_IRQDISABLE 0x80 #define PIRQ_PIC_IRQ3 0x3 #define PIRQ_PIC_IRQ4 0x4 #define PIRQ_PIC_IRQ5 0x5 |