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| author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2018-03-29 14:43:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-24 14:03:47 +0000 |
| commit | 2f66c709f481aec055809ac30afea094f036a136 (patch) | |
| tree | b1d6d63ddc84573d9288224a3854a0fb6cf12b85 /src/soc | |
| parent | ab1227226ebd78b40783cb200e60711b900352f0 (diff) | |
| download | coreboot-2f66c709f481aec055809ac30afea094f036a136.tar.xz | |
soc/intel/denverton_ns: Enable Fast Strings
Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25431
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/denverton_ns/cpu.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/msr.h | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 676fab7cbd..f954411ff2 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 - 2017 Intel Corp. + * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -39,6 +40,11 @@ static void denverton_core_init(struct device *cpu) printk(BIOS_DEBUG, "Init Denverton-NS SoC cores.\n"); + /* Enable Fast Strings */ + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= FAST_STRINGS_ENABLE_BIT; + wrmsr(IA32_MISC_ENABLE, msr); + /* Enable Turbo */ enable_turbo(); diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 165856fd7c..825d4cfca8 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -92,6 +92,7 @@ #define PRMRR_SUPPORTED (1 << 12) /* IA32_MISC_ENABLE bits */ +#define FAST_STRINGS_ENABLE_BIT (1 << 0) #define SPEED_STEP_ENABLE_BIT (1 << 16) /* Read BCLK from MSR */ |