diff options
| author | Weiyi Lu <weiyi.lu@mediatek.com> | 2019-11-22 12:00:24 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-26 11:50:05 +0000 |
| commit | 433acc2d3d6cfb3d16030cbba7be9a5defccf057 (patch) | |
| tree | 0235a8ccf42e87f42263a91ecf276bddadaa7cc3 /src/soc | |
| parent | 026863b2ffa132e1f206a86b3fbf9360c86138d3 (diff) | |
| download | coreboot-433acc2d3d6cfb3d16030cbba7be9a5defccf057.tar.xz | |
soc/mediatek/mt8183: disable BBLPM of DCXO core
When we only enable XO_SOC and mask most BBLPM requests, the BBLPM HW
arbiter will have DCXO core to enter Baseband Low-Power Mode(BBLPM).
Under BBLPM mode, inaccurate(about 1.5KHz offset) 26MHz clocks from
crystal is provided and crystal voltage will drop from 1.8V to 0.7V
or lower.
In order to ensure the stability by always outputting an accuarate
system clock when system is running. We should disable BBLPM when only
XO_SOC enabled.
BRANCH=kukui
TEST=accurate 26MHz provided and correct crystal voltage swing
Change-Id: Iea72a964507a19735cf92e3774cd8a94c06545b2
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37136
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/mediatek/mt8183/rtc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 19b717cc82..6e17a309fe 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -435,8 +435,8 @@ void mt6358_dcxo_disable_unused(void) { /* Disable clock buffer XO_CEL */ rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800); - /* Mask bblpm */ - rtc_write(PMIC_RG_DCXO_CW23, 0x0053); + /* Mask bblpm request and switch off bblpm mode */ + rtc_write(PMIC_RG_DCXO_CW23, 0x0052); } /* the rtc boot flow entry */ |