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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-09-26 14:00:14 +0200 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2019-10-15 08:19:31 +0000 |
| commit | 5199e826db9a1c963893664270a6de3184e3de41 (patch) | |
| tree | 6fe3f3e3b347d2a908f98678620e845b74566140 /src/soc | |
| parent | 05bad430b65ca626c8e819cdeda4ffe2a9b6feb3 (diff) | |
| download | coreboot-5199e826db9a1c963893664270a6de3184e3de41.tar.xz | |
soc/intel/skylake/chip: Unhide P2SB device
APL unhides the P2SB device in coreboot already. Do the same on SKL/KBL.
As the coreboot PCI allocator needs to be able to find the device,
unhide it after FSP-S.
The device is hidden in the SoC finalize function already and not visible
in the OS, as more P2SB device IDs have been added.
Other SoCs aren't updated, because they are too broken.
Fixes "BUG: XXX requests hidden ...." warnings in coreboot log.
Tested on Supermicro X11SSH-TF.
Change-Id: I0d14646098c34d3bf5cd49c35dcfcdce2c57431d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/skylake/finalize.c | 13 |
2 files changed, 12 insertions, 9 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 55fedd3cf5..c4f4e50cd2 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -28,6 +28,7 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/mp_init.h> #include <intelblocks/xdci.h> +#include <intelblocks/p2sb.h> #include <intelpch/lockdown.h> #include <romstage_handoff.h> #include <soc/acpi.h> @@ -175,6 +176,13 @@ void soc_init_pre_device(void *chip_info) /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume()); + /* + * Keep the P2SB device visible so it and the other devices are + * visible in coreboot for driver support and PCI resource allocation. + * There is no UPD setting for this. + */ + p2sb_unhide(); + /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 0d6f7370a5..4cc9c8362b 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -46,14 +46,6 @@ #define PCR_PSFX_T0_SHDW_PCIEN 0x1C #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) -static void disable_sideband_access(void) -{ - p2sb_disable_sideband_access(); - - /* hide p2sb device */ - p2sb_hide(); -} - static void pch_disable_heci(void) { /* unhide p2sb device */ @@ -63,7 +55,7 @@ static void pch_disable_heci(void) pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); - disable_sideband_access(); + p2sb_disable_sideband_access(); } static void pch_finalize_script(struct device *dev) @@ -113,6 +105,9 @@ static void pch_finalize_script(struct device *dev) /* we should disable Heci1 based on the devicetree policy */ if (config->HeciEnabled == 0) pch_disable_heci(); + + /* Hide p2sb device as the OS must not change BAR0. */ + p2sb_hide(); } static void soc_lockdown(struct device *dev) |