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| author | Paul Kocialkowski <contact@paulk.fr> | 2016-05-07 14:31:35 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-05-09 07:45:18 +0200 |
| commit | 536f5a7eb9c8332ec4e0e0058cdd532a364caadd (patch) | |
| tree | ee18f6e0efb08c4d07a5bce53713509897f0f66b /src/soc | |
| parent | 30554c8416b1ec3c71fbf6c8269d7e978178b919 (diff) | |
| download | coreboot-536f5a7eb9c8332ec4e0e0058cdd532a364caadd.tar.xz | |
tegra132, tegra210: Fix "becasue" typo in comments
This renames "becasue" occurrences to "because".
Change-Id: I7862ce6a865cb1525ca1cef69c2eb1e90cc76a9d
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/14735
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/nvidia/tegra132/dc.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/dc.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra132/dc.c b/src/soc/nvidia/tegra132/dc.c index 3ae25bc2f5..fd36c9827b 100644 --- a/src/soc/nvidia/tegra132/dc.c +++ b/src/soc/nvidia/tegra132/dc.c @@ -138,7 +138,7 @@ void update_display_shift_clock_divider(struct display_controller *disp_ctrl, * set up window registers and activate window except two: * frame buffer base address register (WINBUF_START_ADDR) and * display enable register (_DISP_DISP_WIN_OPTIONS). This is - * becasue framebuffer is not available until payload stage. + * because framebuffer is not available until payload stage. */ void update_window(const struct soc_nvidia_tegra132_config *config) { diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index 88e599defd..39f9be0491 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -138,7 +138,7 @@ void update_display_shift_clock_divider(struct display_controller *disp_ctrl, * set up window registers and activate window except two: * frame buffer base address register (WINBUF_START_ADDR) and * display enable register (_DISP_DISP_WIN_OPTIONS). This is - * becasue framebuffer is not available until payload stage. + * because framebuffer is not available until payload stage. */ void update_window(const struct soc_nvidia_tegra210_config *config) { |