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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-17 16:32:24 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-18 14:55:35 +0000 |
| commit | 569887a64084f18da1daf55ff0f10a855bb537c8 (patch) | |
| tree | ca09e087af5ee5da84491f3baa08813cf5e61654 /src/soc | |
| parent | fb57d7c54931376a2ec751df521954b900e7730c (diff) | |
| download | coreboot-569887a64084f18da1daf55ff0f10a855bb537c8.tar.xz | |
soc/intel/common: lpc/espi: fix wrong lock bit
This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance
with doc#332691-003EN and doc#334819-001.
Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/lpc/lpc_def.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index c066f68f17..9a72580af6 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -37,7 +37,7 @@ #define LPC_LGMR_WINDOW_SIZE (64 * KiB) #define LPC_BIOS_CNTL 0xdc #define LPC_BC_BILD (1 << 7) /* BILD */ -#define LPC_BC_LE (1 << 2) /* LE */ +#define LPC_BC_LE (1 << 1) /* LE */ #define LPC_BC_EISS (1 << 5) /* EISS */ #define LPC_PCCTL 0xE0 /* PCI Clock Control */ #define LPC_PCCTL_CLKRUN_EN (1 << 0) |