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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-12 14:01:13 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-15 17:56:36 +0000 |
| commit | 56f768774a25320d738febf99c335abdb6eeafbe (patch) | |
| tree | 4c6def307e71cc2d096c5152d86c6d396e09ea73 /src/soc | |
| parent | 724c66c88fa219087f4d6a0ccce1ba1d6f93c93b (diff) | |
| download | coreboot-56f768774a25320d738febf99c335abdb6eeafbe.tar.xz | |
soc/intel/broadwell: Use the common cpu/intel/car romstage entry
The only functional difference is the use of stack guards.
Change-Id: I95645271e0d93a97f544a1cc4e9a4320738e6a20
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 23 |
2 files changed, 5 insertions, 19 deletions
diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index 2d562d98ef..cc0a05124f 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,5 +1,6 @@ cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += cpu.c romstage-y += pch.c romstage-y += power_state.c diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index acbca14a88..25c47c62c2 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -21,6 +21,7 @@ #include <bootmode.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <elog.h> #include <program_loading.h> @@ -39,7 +40,7 @@ /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ -static void platform_enter_postcar(void) +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; @@ -63,8 +64,8 @@ static void platform_enter_postcar(void) run_postcar_phase(&pcf); } -/* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc, uint32_t bist) +/* Entry from cpu/intel/car/romstage.c. */ +void mainboard_romstage_entry(unsigned long bist) { struct romstage_params rp = { .bist = bist, @@ -72,12 +73,6 @@ static void romstage_main(uint64_t tsc, uint32_t bist) post_code(0x30); - /* Save initial timestamp from bootblock. */ - timestamp_init(tsc); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - /* System Agent Early Initialization */ systemagent_early_init(); @@ -131,16 +126,6 @@ static void romstage_main(uint64_t tsc, uint32_t bist) romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3); mainboard_post_raminit(&rp); - - platform_enter_postcar(); -} - -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - romstage_main(base_timestamp, bist); } void __weak mainboard_pre_console_init(void) {} |