diff options
| author | Julius Werner <jwerner@chromium.org> | 2020-04-29 15:35:17 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-04-30 01:18:11 +0000 |
| commit | 6f028e7993aaca3a7557f096fa36c0b848e42016 (patch) | |
| tree | 1245dcebb8fbaa601201f88783ce9306edfc4b97 /src/soc | |
| parent | 26afd648a1969df55a5786a2c877eec5144400ae (diff) | |
| download | coreboot-6f028e7993aaca3a7557f096fa36c0b848e42016.tar.xz | |
sc7180: Increase SPI flash frequency to 37.5MHz
It seems that all SC7180 boards we have can well handle 37.5MHz of SPI
flash speed, so bump that up from the current 25MHz so that we don't
leave boot speed on the table. (The next step would be 50MHz which
currently doesn't work on all boards so we're not going there yet.)
BUG=b:117440651
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id6e98fcbc89f5f3bfa408c7e8bbc90b4c92ceeea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/qualcomm/sc7180/bootblock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index 9cecb4f4f5..d860c4a5fd 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -22,6 +22,6 @@ void bootblock_soc_init(void) { sc7180_mmu_init(); clock_init(); - quadspi_init(25 * MHz); + quadspi_init(37500 * KHz); qupv3_fw_init(); } |