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| author | Thejaswani Putta <thejaswani.putta@intel.com> | 2019-04-11 18:36:08 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-23 09:56:37 +0000 |
| commit | 6f5225c7e0ad7a373af1decc212cde5c33b00730 (patch) | |
| tree | 794593f84299c9258953eb34fdd39ecee39a1f20 /src/soc | |
| parent | 21f9b3ecd7babefa51f497bd61495316ebf41851 (diff) | |
| download | coreboot-6f5225c7e0ad7a373af1decc212cde5c33b00730.tar.xz | |
Klocwork: Fix the Null pointer derefernce found by klocwork
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I15973ac28e9645826986cf63d2160eedb83024e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32290
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/ramstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index e1883f2ecd..706536940d 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -23,6 +23,7 @@ #include <soc/ramstage.h> #include <soc/intel/broadwell/chip.h> #include <soc/intel/common/acpi.h> +#include <assert.h> /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) @@ -31,6 +32,8 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) static uint32_t gpe0_sts[GPE0_REG_MAX]; int i; + assert(ps != NULL); + *pm1 = ps->pm1_sts & ps->pm1_en; /* Mask off GPE0 status bits that are not enabled */ |