src/soc/amd/stoneyridge: Remove IMC support

Per AMD, the Integrated Micro Controller is not a supported feature of
the Stoney Ridge APU.  Systems are expected to implement an external EC
for desired features. Remove all stoney IMC files and functions from
src/soc/amd/stoneyridge.

There are 2 "IMC bits" left (and used) that are not truly IMC. New BKDG
describe these bits, so a new patch will be released later to fix the
names and comment.

BUG=b:111780177
TEST=Build grunt and gardenia

Change-Id: I6a24e4c3f03d04713a030b884c611d9c64c4cb3a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27651
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

14 files changed, 1 insertions, 255 deletions

diff --git a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h
index 97bf2082d3..3d5ae8f2f9 100644
--- a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h
+++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h
@@ -64,7 +64,6 @@ AGESA_STATUS agesa_HaltThisAp(UINT32 Func, UINTN Data, VOID *ConfigPtr);
 
 void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset);
 void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env);
-void oem_fan_control(FCH_DATA_BLOCK *FchParams);
 AGESA_STATUS platform_PcieSlotResetControl(UINT32 Func, UINTN Data,
 	VOID *ConfigPtr);
 typedef struct {
diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c
index d2f7a32618..430dc45ba3 100644
--- a/src/soc/amd/stoneyridge/BiosCallOuts.c
+++ b/src/soc/amd/stoneyridge/BiosCallOuts.c
@@ -58,9 +58,6 @@ AGESA_STATUS agesa_fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
 		FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
 		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
 
-		if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
-			oem_fan_control(FchParams_env);
-
 		/* XHCI configuration */
 		if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE))
 			FchParams_env->Usb.Xhci0Enable = TRUE;
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 05c3043282..7675bce0a7 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -171,12 +171,6 @@ config STONEYRIDGE_XHCI_FWM
 	help
 	  Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0
 
-config STONEYRIDGE_IMC_FWM
-	bool "Add IMC firmware"
-	default n
-	help
-	  Add Stoney Ridge IMC Firmware to support the onboard fan control
-
 config STONEYRIDGE_GEC_FWM
 	bool
 	default n
@@ -189,11 +183,6 @@ config STONEYRIDGE_XHCI_FWM_FILE
 	default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin"
 	depends on STONEYRIDGE_XHCI_FWM
 
-config STONEYRIDGE_IMC_FWM_FILE
-	string "IMC firmware path and filename"
-	default "3rdparty/blobs/soc/amd/stoneyridge/imc.bin"
-	depends on STONEYRIDGE_IMC_FWM
-
 config STONEYRIDGE_GEC_FWM_FILE
 	string "GEC firmware path and filename"
 	depends on STONEYRIDGE_GEC_FWM
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 5df4889553..bf5724f48a 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -57,7 +57,6 @@ romstage-y += i2c.c
 romstage-y += romstage.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 romstage-y += gpio.c
-romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
 romstage-y += monotonic_timer.c
 romstage-y += pmutil.c
 romstage-y += reset.c
@@ -100,7 +99,6 @@ ramstage-y += hda.c
 ramstage-y += monotonic_timer.c
 ramstage-y += southbridge.c
 ramstage-y += sb_util.c
-ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
 ramstage-y += lpc.c
 ramstage-y += northbridge.c
 ramstage-y += pmutil.c
@@ -200,7 +198,6 @@ endif
 add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
 
 OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci)
-OPT_STONEYRIDGE_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_IMC_FWM_FILE), --imc)
 OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILEddd), --gec)
 
 OPT_2AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey2)
@@ -222,7 +219,6 @@ OPT_2SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --smuf
 
 
 $(obj)/amdfw.rom:	$(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \
-			$(call strip_quotes, $(CONFIG_STONEYRIDGE_IMC_FWM_FILE)) \
 			$(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \
 			$(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \
 			$(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \
@@ -243,7 +239,6 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \
 	@printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
 	$(AMDFWTOOL) \
 		$(OPT_STONEYRIDGE_XHCI_FWM_FILE) \
-		$(OPT_STONEYRIDGE_IMC_FWM_FILE) \
 		$(OPT_STONEYRIDGE_GEC_FWM_FILE) \
 		$(OPT_AMD_PUBKEY_FILE) \
 		$(OPT_PSPBTLDR_FILE) \
diff --git a/src/soc/amd/stoneyridge/acpi/AmdImc.asl b/src/soc/amd/stoneyridge/acpi/AmdImc.asl
deleted file mode 100644
index 519b05cf37..0000000000
--- a/src/soc/amd/stoneyridge/acpi/AmdImc.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-//BTDC Due to IMC Fan, ACPI control codes
-OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
-Field(IMIO , ByteAcc, NoLock, Preserve) {
-	IMCX,8,
-	IMCA,8
-}
-
-IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
-	Offset(0x80),
-	MSTI, 8,
-	MITS, 8,
-	MRG0, 8,
-	MRG1, 8,
-	MRG2, 8,
-	MRG3, 8,
-}
-
-Method(WACK, 0)
-{
-	Store(0, Local0)
-	While (LNotEqual(Local0, 0xFA)) {
-		Store(MRG0, Local0)
-		Sleep(10)
-	}
-}
-
-//Init
-Method (ITZE, 0)
-{
-	Store(0, MRG0)
-	Store(0xB5, MRG1)
-	Store(0, MRG2)
-	Store(0x96, MSTI)
-	WACK()
-
-	Store(0, MRG0)
-	Store(0, MRG1)
-	Store(0, MRG2)
-	Store(0x80, MSTI)
-	WACK()
-
-	Or(MRG2, 0x01, Local0)
-
-	Store(0, MRG0)
-	Store(0, MRG1)
-	Store(Local0, MRG2)
-	Store(0x81, MSTI)
-	WACK()
-}
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
index e767fddbc9..81964baa48 100644
--- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
@@ -130,10 +130,6 @@ Method(_CRS, 0) {
 	Return(CRES) /* note to change the Name buffer */
 } /* end of Method(_SB.PCI0._CRS) */
 
-#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)
-	#include "acpi/AmdImc.asl"
-#endif
-
 /*
  *
  *               FIRST METHOD CALLED UPON BOOT
@@ -158,12 +154,6 @@ Method(_INI, 0) {
 
 	/* Determine the OS we're running on */
 	OSFL()
-
-#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)
-#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)
-	ITZE() /* enable IMC Fan Control*/
-#endif
-#endif
 } /* End Method(_SB._INI) */
 
 Method(OSFL, 0){
diff --git a/src/soc/amd/stoneyridge/imc.c b/src/soc/amd/stoneyridge/imc.c
deleted file mode 100644
index 5d883d99ba..0000000000
--- a/src/soc/amd/stoneyridge/imc.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define __SIMPLE_DEVICE__
-
-#include <amdblocks/agesawrapper.h>
-#include <soc/imc.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <delay.h>
-
-#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE)
-
-void imc_reg_init(void)
-{
-	u8 reg8;
-	/* Init Power Management Block 2 (PM2) Registers.
-	 * Check BKDG for AMD Family 16h for details. */
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x00), 0x06);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x01), 0x06);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x02), 0xf7);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x03), 0xff);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x04), 0xff);
-
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x10), 0x06);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x11), 0x06);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x12), 0xf7);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x13), 0xff);
-	write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x14), 0xff);
-
-	reg8 = pci_read_config8(PCI_DEV(0, 0x18, 0x3), 0x1e4);
-	reg8 &= 0x8f;
-	reg8 |= 0x10;
-	pci_write_config8(PCI_DEV(0, 0x18, 0x3), 0x1e4, reg8);
-}
-
-void enable_imc_thermal_zone(void)
-{
-	AMD_CONFIG_PARAMS StdHeader;
-	UINT8 FunNum;
-	UINT8 regs[10];
-	int i;
-
-	regs[0] = 0;
-	regs[1] = 0;
-	FunNum = Fun_80;
-	for (i = 0 ; i <= 1 ; i++)
-		WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
-	WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader);
-	WaitForEcLDN9MailboxCmdAck(&StdHeader);
-
-	for (i = 2 ; i < ARRAY_SIZE(regs) ; i++)
-		ReadECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
-
-	/* enable thermal zone 0 */
-	regs[2] |= 1;
-	regs[0] = 0;
-	regs[1] = 0;
-	FunNum = Fun_81;
-	for (i = 0 ; i < ARRAY_SIZE(regs) ; i++)
-		WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
-	WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader);
-	WaitForEcLDN9MailboxCmdAck(&StdHeader);
-}
-
-void imc_sleep(void)
-{
-	ImcSleep(NULL);
-}
-
-void imc_wakeup(void)
-{
-	ImcWakeup(NULL);
-}
diff --git a/src/soc/amd/stoneyridge/include/fchec.h b/src/soc/amd/stoneyridge/include/fchec.h
deleted file mode 100644
index 80125ecaad..0000000000
--- a/src/soc/amd/stoneyridge/include/fchec.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __AMD_STONEY_FCHEC__
-#define __AMD_STONEY_FCHEC__
-
-#include <amdblocks/agesawrapper.h>
-#include <soc/imc.h>
-
-void agesawrapper_fchecfancontrolservice(void);
-
-#endif
diff --git a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h
index e160c89283..beef2bcc81 100644
--- a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h
+++ b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h
@@ -47,12 +47,6 @@
 #define PIRQ_PMON	0x16	/* Performance Monitor */
 #define PIRQ_SD		0x17	/* SD */
 #define PIRQ_SDIO	0x1a	/* SDIO */
-#define PIRQ_IMC0	0x20	/* IMC INT0 */
-#define PIRQ_IMC1	0x21	/* IMC INT1 */
-#define PIRQ_IMC2	0x22	/* IMC INT2 */
-#define PIRQ_IMC3	0x23	/* IMC INT3 */
-#define PIRQ_IMC4	0x24	/* IMC INT4 */
-#define PIRQ_IMC5	0x25	/* IMC INT5 */
 #define PIRQ_EHCI	0x30	/* USB EHCI	12h.0 */
 #define PIRQ_XHCI	0x34	/* USB XHCI	10h.0 */
 #define PIRQ_SATA	0x41	/* SATA		11h.0 */
diff --git a/src/soc/amd/stoneyridge/include/soc/imc.h b/src/soc/amd/stoneyridge/include/soc/imc.h
deleted file mode 100644
index 079df79dc4..0000000000
--- a/src/soc/amd/stoneyridge/include/soc/imc.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __STONEYRIDGE_IMC_H__
-#define __STONEYRIDGE_IMC_H__
-
-void imc_reg_init(void);
-void enable_imc_thermal_zone(void);
-void imc_sleep(void);
-void imc_wakeup(void);
-
-#endif
diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h
index 636f9c3559..24543516c2 100644
--- a/src/soc/amd/stoneyridge/include/soc/smi.h
+++ b/src/soc/amd/stoneyridge/include/soc/smi.h
@@ -125,7 +125,6 @@
 #define SMITYPE_USB_SMI				76
 #define SMITYPE_SERIRQ				77
 #define SMITYPE_SMBUS0_INTR			78
-#define SMITYPE_IMC				79
 #define SMITYPE_XHC_ERROR			80
 #define SMITYPE_INTRUDER			81
 #define SMITYPE_VBAT_LOW			82
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 2e953091f8..ece78b625e 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -110,9 +110,6 @@
 #define   SPI_PRESERVE_BITS		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
 
 #define LPC_PCI_CONTROL			0x40
-#define   IMC_PRESENT			BIT(7)
-#define   IMC_TO_HOST_SEMAPHORE		BIT(6)
-#define   HOST_TO_IMC_SEMAPHORE		BIT(5)
 #define   LEGACY_DMA_EN			BIT(2)
 
 #define LPC_IO_PORT_DECODE_ENABLE	0x44
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 18e6c6c59d..63d8806fd0 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -25,10 +25,10 @@
 #include <cbmem.h>
 #include <elog.h>
 #include <amdblocks/amd_pci_util.h>
+#include <amdblocks/agesawrapper.h>
 #include <soc/southbridge.h>
 #include <soc/smi.h>
 #include <soc/amd_pci_int_defs.h>
-#include <fchec.h>
 #include <delay.h>
 #include <soc/pci_devs.h>
 #include <agesa_headers.h>
@@ -123,12 +123,6 @@ const static struct irq_idx_name irq_association[] = {
 	{ PIRQ_PMON,	"PerMon" },
 	{ PIRQ_SD,	"SD" },
 	{ PIRQ_SDIO,	"SDIOt" },
-	{ PIRQ_IMC0,	"IMC INT0" },
-	{ PIRQ_IMC1,	"IMC INT1" },
-	{ PIRQ_IMC2,	"IMC INT2" },
-	{ PIRQ_IMC3,	"IMC INT3" },
-	{ PIRQ_IMC4,	"IMC INT4" },
-	{ PIRQ_IMC5,	"IMC INT5" },
 	{ PIRQ_EHCI,	"EHCI" },
 	{ PIRQ_XHCI,	"XHCI" },
 	{ PIRQ_SATA,	"SATA" },
@@ -766,11 +760,6 @@ void southbridge_final(void *chip_info)
 {
 	uint8_t restored_power = PM_S5_AT_POWER_RECOVERY;
 
-	if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) {
-		agesawrapper_fchecfancontrolservice();
-		if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE))
-			enable_imc_thermal_zone();
-	}
 	if (IS_ENABLED(CONFIG_MAINBOARD_POWER_RESTORE))
 		restored_power = PM_RESTORE_S0_IF_PREV_S0;
 	pm_write8(PM_RTC_SHADOW, restored_power);
diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c
index 718ad94bec..9baf43397e 100644
--- a/src/soc/amd/stoneyridge/spi.c
+++ b/src/soc/amd/stoneyridge/spi.c
@@ -29,7 +29,6 @@
 #include <device/pci_ops.h>
 #include <soc/southbridge.h>
 #include <soc/pci_devs.h>
-#include <soc/imc.h>
 
 #define SPI_DEBUG_DRIVER IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
 
@@ -169,15 +168,11 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 
 int chipset_volatile_group_begin(const struct spi_flash *flash)
 {
-	if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
-		imc_sleep();
 	return 0;
 }
 
 int chipset_volatile_group_end(const struct spi_flash *flash)
 {
-	if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
-		imc_wakeup();
 	return 0;
 }