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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-01-07 10:54:36 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-01-14 09:12:41 +0000 |
| commit | 79131f8323e042165646991d88769f8a6a028924 (patch) | |
| tree | 3b79341315c0bb598432fad3dda174c48b04af20 /src/soc | |
| parent | 7d9016931c20d8c990a8df26f44e445e4a24f3c4 (diff) | |
| download | coreboot-79131f8323e042165646991d88769f8a6a028924.tar.xz | |
soc/intel/fsp_broadwell_de: Fix uart
* Disable FSP serial output if not CONSOLE_SERIAL
Tested on wedge100s.
Change-Id: Idd825d2d6eb423452d3e81265860205980f6aa5b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index 800f68653b..b64efce4ae 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -66,6 +66,9 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) UpdData->SerialPortBaudRate = 12; } + if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + UpdData->SerialPortType = 0; + /* * Memory Down */ |