diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-04 20:32:15 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-11 11:42:26 +0000 |
| commit | 8245bd25a35466248c00bc7a4d0cf96f8391924a (patch) | |
| tree | 5e3cc97038c161661fdaa0015ad37f1d73f4219c /src/soc | |
| parent | ad27283a3c777f288254974cac233e47d1c0005d (diff) | |
| download | coreboot-8245bd25a35466248c00bc7a4d0cf96f8391924a.tar.xz | |
fmap: Make FMAP_CACHE mandatory if it is configured in
Now that we have a CONFIG_NO_FMAP_CACHE to completely configure out the
pre-RAM FMAP cache code, there's no point in allowing the region to be
optional anymore. This patch makes the section required by the linker.
If a board doesn't want to provide it, it has to select NO_FMAP_CACHE.
Adding FMAP_CACHE regions to a couple more targets that I think can use
them but I don't know anything about... please yell if one of these is
a bad idea and I should mark them NO_FMAP_CACHE instead.
Change-Id: Ic7d47772ab3abfa7e3a66815c3739d0af071abc2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/cavium/cn81xx/include/soc/memlayout.ld | 3 | ||||
| -rw-r--r-- | src/soc/qualcomm/sdm845/include/soc/memlayout.ld | 3 | ||||
| -rw-r--r-- | src/soc/sifive/fu540/include/soc/memlayout.ld | 1 |
3 files changed, 5 insertions, 2 deletions
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index e4e3490395..1a0eb155b7 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -31,7 +31,8 @@ SECTIONS STACK(BOOTROM_OFFSET, 16K) TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K) - PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K) + PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K) + FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K) PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index b0d2d43f4b..c3a3b4c84a 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -57,7 +57,8 @@ SECTIONS TIMESTAMP(0x14836000, 1K) PRERAM_CBMEM_CONSOLE(0x14836400, 32K) PRERAM_CBFS_CACHE(0x1483E400, 70K) - REGION(bsram_unused, 0x1484FC00, 0x9E300, 0x100) + FMAP_CACHE(0x1484FC00, 2K) + REGION(bsram_unused, 0x14850400, 0x9DB00, 0x100) REGION(ddr_information, 0x148EDF00, 256, 256) REGION(limits_cfg, 0x148EE000, 4K, 4K) REGION(qclib_serial_log, 0x148EF000, 4K, 4K) diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index df30ede510..46c559cba1 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -27,6 +27,7 @@ SECTIONS BOOTBLOCK(FU540_L2LIM, 64K) CAR_STACK(FU540_L2LIM + 64K, 20K) PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) + FMAP_CACHE(FU540_L2LIM + 92K, 2K) ROMSTAGE(FU540_L2LIM + 128K, 128K) PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) L2LIM_END(FU540_L2LIM + 2M) |