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| author | Aaron Durbin <adurbin@chromium.org> | 2014-08-04 12:35:32 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-25 22:31:37 +0100 |
| commit | 8c6d34c1f87f7f48f351e9496ec45985208f5076 (patch) | |
| tree | 65931af3fcfb4d7dca8bee8e670c468c0a166bfb /src/soc | |
| parent | dabf0ebec03772cac320dc950cac57a48e1bd3c9 (diff) | |
| download | coreboot-8c6d34c1f87f7f48f351e9496ec45985208f5076.tar.xz | |
ryu: Add 4 LPDDR3 SDRAM BCTs
These are used by the LPDDR3 code in sdram.c.
Based on the schematic and email, I've filled in 4 slots
in sdram_configs.c. My A44 returns RAMCODE 0 (using only bits
1:0) for Samsung SDRAM. I haven't tested the other 2 types of
RAM (Hynix and Micron). The 4th slot is a fallback slow Micron
config.
Previously existing configurations were dropped.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built for rush and rush_ryu.
Change-Id: I55a737db269fe5fac1565d58bd8f8afcbc5beecb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9a431466171a85a5c8151e7466eb5f77862e7b44
Original-Change-Id: If216096ffc9e9836b6d082ad0668640b3eec37b7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id: a45e7788dd78697ac5f48b6cc64108ca0e4912dd
Original-Change-Id: Ib7e8b814eb6dadb9b366536721876a3eeba0d2c0
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216000
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8976
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
0 files changed, 0 insertions, 0 deletions