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| author | Sourabh Banerjee <sbanerje@codeaurora.org> | 2015-01-20 15:18:40 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-13 12:24:09 +0200 |
| commit | 8c916ec8346182b6b2d085d4663be556c376f414 (patch) | |
| tree | 663dfcce37f29d9c85a9e1079984b0a0a2015535 /src/soc | |
| parent | 24d4dae00f5bb2c1d921ec28726826ddaa3e1564 (diff) | |
| download | coreboot-8c916ec8346182b6b2d085d4663be556c376f414.tar.xz | |
tpm: wait for valid bit to be set in TPM access register before using tpm
As per the TCG PC Client TPM Interface Specification v1.2, bit 7 of the
access register (tmpRegValiSts bit) stays "0" until the TPM has complete
through self test and initialization. This bit is set "1" to indicate that
the other bits in the register are valid.
BRANCH=chromeos-2013.04
BUG=chrome-os-partner:35328
TEST=Booted up storm p0.2 and whirwind sp3.
Verified TPM chip is detected and reported in coreboot logs.
Change-Id: I1049139fc155bfd2e1f29e3b8a7b9d2da6360857
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 006fc93c6308d6f3fa220f00708708aa62cc676c
Original-Change-Id: I9df3388ee1ef6e4a9d200d99aea1838963747ecf
Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242222
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9567
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
0 files changed, 0 insertions, 0 deletions