diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2019-07-30 09:53:23 +0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-08-01 16:47:10 +0000 |
| commit | 92dc39129156307913dbf3c07f926554f0c14ab8 (patch) | |
| tree | f7bc788b3964d3c5890e74cb09bdaac2976d52c7 /src/soc | |
| parent | bba18c55403bf3c664683993848eba93b3ec8e24 (diff) | |
| download | coreboot-92dc39129156307913dbf3c07f926554f0c14ab8.tar.xz | |
soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registers
Clear the GPI Interrupt Status & Enable registers to prevent any
interrupt storms due to GPI.
BUG=b:138282962
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot-up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.
Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/bootblock.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 5555969289..30c2266096 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -59,6 +59,11 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { + /* + * Clear the GPI interrupt status and enable registers. These + * registers do not get reset to default state when booting from S5. + */ + gpi_clear_int_cfg(); report_platform_info(); pch_early_init(); } |