soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_init

PMC initialization on Cannon Lake happens earlier in the boot sequence
than other SoCs because FSP-Silicon init hides PMC from PCI bus. As
ACPI disabling was done as part of PMC init, it was being called
earlier than what other SoCs do. This resulted in a different order of
events for some drivers e.g. ChromeOS EC. In case of ChromeOS EC, it
ended up clearing EC events (which happens as part of ACPI disabling
in SMM) before logging any events of interest that happen during
mainboard initialization.

This change moves the call to disable ACPI to pmc_soc_init just like
other SoCs to keep the order of events more aligned.

BUG=b:126016602
TEST=Verified that EC panic event gets logged to eventlog correctly.

Change-Id: Ib73883424a8dfd315893ca712ca86c7c08cee551
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

1 files changed, 18 insertions, 2 deletions

diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index e111e941e6..24ddfee796 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -144,8 +144,6 @@ static void pmc_init(void *unused)
 	/* Initialize power management */
 	pch_power_options(dev);
 
-	pmc_set_acpi_mode();
-
 	config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
 	config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
 	config_deep_sx(config->deep_sx_config);
@@ -159,3 +157,21 @@ static void pmc_init(void *unused)
 * allocate resources.
 */
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL);
+
+void pmc_soc_init(struct device *dev)
+{
+	/*
+	 * PMC initialization happens earlier for this SoC because FSP-Silicon
+	 * init hides PMC from PCI bus. However, pmc_set_acpi_mode, which
+	 * disables ACPI mode doesn't need to happen that early and can be
+	 * delayed till typical pmc_soc_init callback. This ensures that ACPI
+	 * mode disabling happens the same way for all SoCs and hence the
+	 * ordering of events is the same.
+	 *
+	 * This is important to ensure that the ordering does not break the
+	 * assumptions of any other drivers (e.g. ChromeEC) which could be
+	 * taking different actions based on disabling of ACPI (e.g. flushing of
+	 * all EC hostevent bits).
+	 */
+	pmc_set_acpi_mode();
+}