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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-02 23:41:24 +0100 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-01-08 17:53:37 +0000 |
| commit | b5e72b65a79a4bb019dfd9bde65b159f6813f9fa (patch) | |
| tree | 311cd8ab8514aa2c484a7dd5ee28c5c76bc899e9 /src/soc | |
| parent | c9c29264b8c41bc2462d9a9fd2240b5c9350cdc0 (diff) | |
| download | coreboot-b5e72b65a79a4bb019dfd9bde65b159f6813f9fa.tar.xz | |
soc/amd/stoneyridge: Define CONSOLE_UART_BASE_ADDRESS
The build system for the SeaBIOS payload needs this when
DRIVERS_UART_8250MEM is set. Set it to the first uart controller,
which the coreboot code also seems to do.
Fixes: https://ticket.coreboot.org/issues/150
Change-Id: I962f750f89e0352082e0b7415ceaa9bd350fdf0b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index adfb3d21d7..51573fe34f 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -284,6 +284,11 @@ config STONEYRIDGE_UART to FEDC_6FFFh. UART controller 1 registers range from FEDC_8000h to FEDC_8FFFh. +config CONSOLE_UART_BASE_ADDRESS + depends on CONSOLE_SERIAL + hex + default 0xfedc6000 + config SMM_TSEG_SIZE hex default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER |