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authorAaron Durbin <adurbin@chromium.org>2014-08-04 11:40:45 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-03-25 22:31:38 +0100
commitbf534180997889bb5feef45178eaf24ef834241a (patch)
tree6c754221f82178e20da11d6140ae1b295079158c /src/soc
parent8c6d34c1f87f7f48f351e9496ec45985208f5076 (diff)
downloadcoreboot-bf534180997889bb5feef45178eaf24ef834241a.tar.xz
tegra132: output chip information and MTS version
It's helpful to be able to track this information. Therefore dump it in to the console log. BRANCH=None BUG=chrome-os-partner:31126 TEST=Built and ran on rush. Revision information is put out on the console. Change-Id: I22e7d222259c1179b90edda6d7807559357f6725 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 18d318331b696a6a32e0a45b8f903eb740896b02 Original-Change-Id: Ic95382126a6b8929d0998d1c9adfcbd10e90663f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210903 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8905 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/nvidia/tegra/apbmisc.c13
-rw-r--r--src/soc/nvidia/tegra/apbmisc.h11
-rw-r--r--src/soc/nvidia/tegra132/Makefile.inc1
-rw-r--r--src/soc/nvidia/tegra132/soc.c14
4 files changed, 39 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c
index 5983d546d2..3fc0ef7de1 100644
--- a/src/soc/nvidia/tegra/apbmisc.c
+++ b/src/soc/nvidia/tegra/apbmisc.c
@@ -33,3 +33,16 @@ void clamp_tristate_inputs(void)
{
write32(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global);
}
+
+void tegra_revision_info(struct tegra_revision *id)
+{
+ uintptr_t gp_hidrev= (uintptr_t)TEGRA_APB_MISC_BASE + MISC_GP_HIDREV;
+ uint32_t reg;
+
+ reg = read32((void *)(gp_hidrev));
+
+ id->hid_fam = (reg >> 0) & 0x0f;
+ id->chip_id = (reg >> 8) & 0xff;
+ id->major = (reg >> 4) & 0x0f;
+ id->minor = (reg >> 16) & 0x07;
+}
diff --git a/src/soc/nvidia/tegra/apbmisc.h b/src/soc/nvidia/tegra/apbmisc.h
index 2f1811a1dd..38cd527c9f 100644
--- a/src/soc/nvidia/tegra/apbmisc.h
+++ b/src/soc/nvidia/tegra/apbmisc.h
@@ -34,8 +34,19 @@ struct apbmisc {
#define PP_PINMUX_CLAMP_INPUTS (1 << 0)
+enum {
+ MISC_GP_HIDREV = 0x804
+};
+
+struct tegra_revision {
+ int hid_fam;
+ int chip_id;
+ int major;
+ int minor;
+};
void enable_jtag(void);
void clamp_tristate_inputs(void);
+void tegra_revision_info(struct tegra_revision *id);
#endif /* __SOC_NVIDIA_TEGRA_APBMISC_H__ */
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 756560dc44..868da42b9c 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -49,6 +49,7 @@ ramstage-y += i2c.c
ramstage-y += dma.c
ramstage-y += monotonic_timer.c
ramstage-y += padconfig.c
+ramstage-y += ../tegra/apbmisc.c
ramstage-y += ../tegra/gpio.c
ramstage-y += ../tegra/i2c.c
ramstage-y += ../tegra/pinmux.c
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index f4ef92894f..84b05078f2 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -23,6 +23,7 @@
#include <arch/io.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/addressmap.h>
+#include <soc/nvidia/tegra/apbmisc.h>
static void soc_read_resources(device_t dev)
{
@@ -79,7 +80,20 @@ static void enable_tegra132_dev(device_t dev)
dev->ops = &soc_ops;
}
+static void tegra132_init(void *chip_info)
+{
+ struct tegra_revision rev;
+
+ tegra_revision_info(&rev);
+
+ printk(BIOS_INFO, "chip %x rev %02x.%x\n",
+ rev.chip_id, rev.major, rev.minor);
+
+ printk(BIOS_INFO, "MTS build %08x\n", raw_read_aidr_el1());
+}
+
struct chip_operations soc_nvidia_tegra132_ops = {
CHIP_NAME("SOC Nvidia Tegra132")
+ .init = tegra132_init,
.enable_dev = enable_tegra132_dev,
};