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| author | John Zhao <john.zhao@intel.com> | 2017-11-20 16:42:21 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-23 05:00:55 +0000 |
| commit | bfd62fabc9b7b52a2ec5de93749ab01f697a01a7 (patch) | |
| tree | b9abcb7be2e8f8bdad51a3a97e38a583ece7a0d4 /src/soc | |
| parent | 8f06ce35125869f631a3c7a072503103feca227c (diff) | |
| download | coreboot-bfd62fabc9b7b52a2ec5de93749ab01f697a01a7.tar.xz | |
soc/intel/cannonlake: Invoke pmc and hard reset only if CSE fails to reset
If CSE fails to do a global reset with the calling sequence of heci
reset/send/receive, then invoke pmc and hard reset.
TEST= Force global reset from early or late romstage. The function
send_heci_reset_message has the calling sequence of heci reset/send/receive.
It is observed timed out error (associated with heci_receive) occurs
only if global reset is forced during early romstage. If global reset is
trigged at late stage (i.e, after fsp_memory_init), then no timed out error
and CSE handles reset properly.
Change-Id: I5bb12554e5745d7704a1b684a3a51034bb35f787
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22549
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/reset.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index a270a561b8..03f9cb812b 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -80,7 +80,9 @@ static int send_heci_reset_message(void) void do_global_reset(void) { /* Ask CSE to do the global reset */ - send_heci_reset_message(); + if (!send_heci_reset_message()) + return; + /* global reset if CSE fail to reset */ pmc_global_reset_enable(1); hard_reset(); |