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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-26 09:49:00 +0300
committerPatrick Georgi <pgeorgi@google.com>2019-09-30 11:54:34 +0000
commitd2186a3b3f5c092a97bd2b669a846f73441353d9 (patch)
tree7a70192f3e580097d37ded20837844e7dde8af84 /src/soc
parentb56fcfe9b5b49915c1ae00ac06421fca7a7e2308 (diff)
downloadcoreboot-d2186a3b3f5c092a97bd2b669a846f73441353d9.tar.xz
soc/intel/fsp_broadwell_de: Enable SSE and SSE2
Apparently romcc-bootblock just barely built without XMM registers. Change-Id: Ie7b1101f47c2dfb718bef99f8c05f9d575c821cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/fsp_broadwell_de/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig
index 94eff07bab..6c74a749a4 100644
--- a/src/soc/intel/fsp_broadwell_de/Kconfig
+++ b/src/soc/intel/fsp_broadwell_de/Kconfig
@@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP
select SMP
select IOAPIC
+ select SSE2
select UDELAY_TSC
select SUPPORT_CPU_UCODE_IN_CBFS
select INTEL_DESCRIPTOR_MODE_CAPABLE